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參數(shù)資料
| 型號： | 74FR25900SSC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 20 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | FR/FASTR SERIES, MULTIPLEXER, PDSO48 |
| 封裝： | 0.300 INCH, MO-118, SSOP-48 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 49K |
| 代理商： | 74FR25900SSC |
www.fairchildsemi.com
2
7
Functional Description
The 74FR25900 allows 9-bit data to be transferred from
any of three 9-bit I/O ports to either of the two remaining
I/O ports. The device employs latches in all paths for either
transparent or synchronous operation. Readback capability
from any port to itself is also possible.
Data transfer within the 74FR25900 is controlled through
use of the select (S
0
and S
1
) and output-enable (OE
A
, OE
B
and OE
C
) inputs as described in Table 1. Additional control
is available by use of the latch-enable inputs (LEAC, LECA,
LEBC, LECB) allowing either synchronous or transparent
transfers (see Table 2). Table 1 indicates several readback
conditions. By latching data on a given port and initiating
the readback control configuration, previous data may be
read for system verification or diagnostics. This mode may
be useful in implementing system diagnostics.
Data at the port to be readback must be latched prior to
enabling the outputs on that port. If this is not done, a
closed data loop will result causing possible data integrity
problems. Note that the A and B Ports allow readback with-
out affecting any other port. C Port, however, requires inter-
ruption of either A or B Ports to complete its readback path.
PINV controls inversion of the C
8
bit. A LOW on PINV
allows C
8
data to pass unaltered. A HIGH causes inversion
of the data. See Table 3. This feature allows forcing of par-
ity errors for use in system diagnostics. This is particularly
helpful in 486 processor designs as the 486 does not pro-
vide odd/even parity selection internally.
TABLE 1. Datapath Control
Note 1:
Readback operation in latched mode only. Transparent operation
could result in unpredictable results.
TABLE 2. Latch-Enable Control
TABLE 3. PINV Control
Key:
L
=
LOW Voltage
H
=
HIGH Voltage Level
Q
0
=
Output state prior to LExx LOW-to-HIGH transition
Inputs
Function
S
0
L
L
L
H
H
H
X
X
X
X
L
S
1
X
L
O
L
X
O
H
H
H
X
L
OE
A
H
H
H
L
H
L
L
H
L
H
L
OE
B
L
H
H
L
L
L
L
H
H
L
X
OE
C
L
H
L
H
L
L
H
H
H
H
X
Port A to Port C
Port A to Port B
Port A to B
+
C
Port B to Port A
Port B to Port C
Port B to A
+
C
Port C to Port A
Port C to Port B
Port C to A
+
B
Outputs Disabled
(Readback to A)
(Note 1)
(Readback to A or C)
(Note 1)
(Readback to B)
(Note 1)
(Readback to B or C)
(Note 1)
L
H
L
X
L
H
L
X
H
X
H
H
X
H
L
LExx
L
L
H
Input
L
H
X
Output
L
H
Q
0
PINV
C
8
L
H
L
H
A
8
or B
8
L
H
H
L
L
L
H
H
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| 74FR543 | Octal Latched Transceiver with 3-STATE Outputs |
| 74FR543SPC | Octal Latched Transceiver with 3-STATE Outputs |
| 74FR543SC | Octal Latched Transceiver with 3-STATE Outputs |
| 74FR573SC | Octal D-Type Latch with 3-STATE Outputs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74FR25900SSCX | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 9-Bit Multiplexer RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| 74FR543 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal Latched Transceiver with 3-STATE Outputs |
| 74FR543 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74FR543SC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal Latched Transceiver with 3-STATE Outputs |
| 74FR543SCX | 功能描述:總線收發(fā)器 Octal Latched Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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