- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375073 > 74F899SC (FAIRCHILD SEMICONDUCTOR CORP) 9-Bit Latchable Transceiver with Parity Generator/Checker PDF資料下載
參數(shù)資料
| 型號： | 74F899SC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-Bit Latchable Transceiver with Parity Generator/Checker |
| 中文描述： | F/FAST SERIES, 9-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 89K |
| 代理商： | 74F899SC |
www.fairchildsemi.com
2
7
Input Loading/Fan-Out
Pin Descriptions
Functional Description
The 74F899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table).
HIGH/LOW
Pin Names
Description
U.L.
Input I
IH
/I
IL
Output I
OH
/I
OL
20
μ
A/
0.6 mA
3 mA/24 mA
20
μ
A/
0.6 mA
12 mA/64 mA
20
μ
A/
0.6 mA
3 mA/24 mA
20
μ
A/
0.6 mA
12 mA/64 mA
20
μ
A/
0.6 mA
20
μ
A/
0.6 mA
20
μ
A/
0.6 mA
20
μ
A/
0.6 mA
1 mA/20 mA
HIGH/LOW
1.0/1.0
150/40
1.0/1.0
600/106.6
1.0/1.0
150/40
1.0/1.0
600/106.6
1.0/1.0
A
0
–A
7
Data Inputs/
Data Outputs
Data Inputs/
Data Outputs
A Bus Parity
Input/Output
B Bus Parity
Input/Output
Parity Select Input
B
0
–B
7
APAR
BPAR
ODD/EVEN
GBA, GAB
Output Enable Inputs
1.0/1.0
SEL
LEA, LEB
Mode Select Input
1.0/1.0
Latch Enable Inputs
Error Signal Outputs
1.0/1.0
50/33.3
ERRA, ERRB
Pin Names
Description
A
0
–A
7
B
0
–B
7
APAR, BPAR
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN
ODD/EVEN Parity Select, Active LOW for EVEN Parity
GBA, GAB
Output Enables for A or B Bus, Active LOW
SEL
Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode
LEA, LEB
Latch Enables for A and B Latches, HIGH for Transparent Mode
ERRA, ERRB
Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F899SCX | Single 8-bit Bus Transceiver |
| 74FR16540QCX | Dual 8-Bit Buffer/Driver |
| 74FR16540SSCX | SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits |
| 74FR16540SSC | 20 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor |
| 74FR16540 | Ferrite Bead; Outer Diameter:8.7mm; Inner Diameter:0.17"; Package/Case:Tubular; External Width:.343 "; Frequency:100MHz; Impedance:102ohm; Length:0.625" RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F899SC_Q | 功能描述:總線收發(fā)器 9-Bit Latchable Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74F899SCX | 功能描述:總線收發(fā)器 9-Bit Latchable Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74F968 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74-FB5-B | 制造商:NTE Electronics 功能描述: |
| 74-FBC | 制造商:Thomas & Betts 功能描述:WELD NON-GNGBLESWBX-3 1/8" DP |
發(fā)布緊急采購，3分鐘左右您將得到回復。