參數(shù)資料
型號: 74F552QC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Octal Registered Transceiver with Parity and Flags
中文描述: F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQCC28
封裝: 0.450 INCH, PLASTIC, MO-047, LCC-28
文件頁數(shù): 3/8頁
文件大?。?/td> 80K
代理商: 74F552QC
3
www.fairchildsemi.com
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Functional Description
Data applied to the A-inputs are entered and stored in the
R register on the rising edge of the CPR Clock Pulse, pro-
vided that the Clock Enable (CER) is LOW; simultaneously,
the status flip-flop is set and the flag (FR) output goes
HIGH. As the Clock Enable (CER) returns to HIGH, the
data will be held in the R register. These data entered from
the A-inputs will appear at the B Port I/O pins after the Out-
put Enable (OEBR) has gone LOW. When OEBR is LOW,
a parity bit appears at the PARITY pin, which will be set
HIGH when there is an even number of 1s or all 0s at the Q
outputs of the R register. After the data is assimilated, the
receiving system clears the flag FR by changing the signal
at the OEBR pin from LOW-to-HIGH.
Data flow from B-to-A proceeds in the same manner
described for A-to-B flow. A LOW at the CES pin and a
LOW-to-HIGH transition at CPS pin enters the B-input data
and the parity-input data into the S registers and the parity
register respectively and set the flag output FS to HIGH. A
LOW signal at the OEAS pin enables the A Port I/O pins
and a LOW-to-HIGH transition of the OEAS signal clears
the FS flag. When OEAS is LOW, the parity check output
ERROR will be HIGH if there is an odd number of 1s at the
Q outputs of the S registers and the parity register. The flag
FS can be cleared by a LOW-to-HIGH transition of the
OEAS signal.
Register Function Table
(Applies to R or S Register)
Inputs
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
=
Not LOW-to-HIGH Transition
NC
=
No Change
Output Control
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Flag Flip-Flop Function Table
(Applies to R or S Flag Flip-Flop)
Inputs
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
=
Not LOW-to-HIGH Transition
NC
=
No Change
Parity Generation Function
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Parity Check Function
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Internal
Function
D
X
L
H
X
CP
X
CE
H
L
L
L
Q
NC
L
H
NC
Hold Data
Load Data
Keep Old Data
OE
Internal
A or B
Function
Q
X
L
H
Outputs
Z
L
H
H
L
L
Disable Output
Enable Output
Enable Output
Flag
Function
CE
H
L
X
CP
X
OE
Output
NC
H
L
Hold Flag
Set Flag
Clear Flag
X
OEBR
Number of HIGHs in the
Q Outputs of the R Register
X
0, 2, 4, 6, 8
1, 3, 5, 7
Parity Output
H
L
L
Z
H
L
OEAS
Number of HIGHs in
Parity
ERROR
the Q Outputs of the S Register
X
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
Input
X
L
L
H
H
Output
H
L
H
H
L
H
L
L
L
L
相關(guān)PDF資料
PDF描述
74F552QCX Single 8-bit Bus Transceiver
74F552SCX Single 8-bit Bus Transceiver
74F552SC Octal Registered Transceiver with Parity and Flags
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74F563PC Octal D-Type Latch with 3-STATE Outputs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74F552QCX 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Single 8-bit Bus Transceiver
74F552SC 功能描述:總線收發(fā)器 Oct Registered Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74F552SCX 功能描述:總線收發(fā)器 Oct Registered Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74F563 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal D-Type Latch with 3-STATE Outputs
74F563 WAF 制造商:Fairchild Semiconductor Corporation 功能描述: