
Philips Semiconductors
Product specification
74F552
Octal registered transceiver with parity and flags (3-State)
1991 Jan 02
3
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0–A7
A Data inputs
3.5/1.0
70
μ
A/0.6mA
B0–B7
B Data inputs
3.5/1.0
70
μ
A/0.6mA
CPR
R registers clock input (active rising edge)
1.0/1.0
20
μ
A/0.6mA
CPS
S registers clock input (active rising edge)
1.0/1.0
20
μ
A/0.6mA
CER
R registers clock Enable input (active Low)
1.0/1.0
20
μ
A/0.6mA
CES
S registers clock Enable input (active Low)
1.0/1.0
20
μ
A/0.6mA
OEBR
A-to-B Output Enable input (active Low)
and clear FS output (active Low)
1.0/2.0
20
μ
A/1.2mA
OEAS
B-to-A Output Enable input (active Low)
and clear FR output (active Low)
1.0/2.0
20
μ
A/1.2mA
PARITY
Parity bit transceiver input
3.5/1.0
70
μ
A/0.6mA
Parity bit transceiver output
750/106.7
15mA/64mA
ERROR
Parity check output (active Low)
50/33.3
1.0mA/20mA
A0–A7
A Data outputs
150/40
3.0mA/24mA
B0–B7
B Data outputs
750/106.7
15mA/64mA
FR
A-to-B Status Flag output (active High)
50/33.3
1.0mA/20mA
FS
B-to-A Status Flag output (active High)
50/33.3
1.0mA/20mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
FUNCTIONAL DESCRIPTION
Data applied to the A inputs are entered and stored on the rising
edge of the CPR clock pulse, provided that the CER is Low;
simultaneously, the status flip-flop is set and the A-to-B flag (FR)
output goes High. As the CER returns to High, the data will be held
in R register. This data entered from the A inputs will appear at the B
port I/O pins after the OEBR has gone Low. When OEBR is Low, a
parity bit appears at the PARITY pin, which will be set High when
there is an even number of 1s or all 0s at the Q outputs of the R
register. After the data is assimilated, the receiving system clears
the flag FR, by changing the signal at the OEBR pin from Low to
High. Data flow from B-to-A proceeds in the same manner described
for A-to-B flow. A Low at the CES pin and a Low-to-High transition at
the CPS pin enters the B input data and the parity input data into the
S register and the parity register respectively and set the flag output
FS to High. A Low signal at the OEAS pin enables the A port I/O
pins and a Low-to-High transition of the OEAS signal clears the FS
flag. When OEAS is Low, the parity check output ERROR will be
High if there is an odd number of 1s at the Q outputs of the S
register and the parity register.
R or S REGISTER FUNCTION TABLE
INPUTS
CPX
OUTPUTS
INTERNAL Q
OPERATING
MODE
An or Bn
CEX
X
X
H
NC
Hold data
L
H
↑
↑
↑
L
L
L
H
Load data
X
L
NC
Keep old data
H = High voltage level
L = Low voltage level
NC= No change
X = Don’t care
X
=
R
or
S
for
CPX
and
CEX
↑
= Low-to-High transition
↑
= Not Low-to-High transition
OUTPUT CONTROL TABLE
INPUT
OEXX
OUTPUTS
OPERATING
MODE
INTERNAL Q
An or Bn
H
X
Z
Disable outputs
L
L
L
H
L
H
Enable outpus
H = High voltage level
L = Low voltage level
X = Don’t care
XX
=
AS
or
BR
Z = High impedance “off” state