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參數(shù)資料
| 型號(hào)： | 74F5074 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Synchronizing dual D-type flip-flop/clock driver(同步雙D觸發(fā)器/時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 同步雙D型flip-flop/clock驅(qū)動(dòng)程序（同步雙?觸發(fā)器/時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | 74F5074 |
Philips Semiconductors
Product specification
74F5074
Synchronizing dual D-type flip-flop/clock driver
2
September 14, 1990
853-1391 00419
FEATURES
Metastable immune characteristics
Output skew guaranteed less than 1.5ns
High source current (I
OH
= 15mA) ideal for clock driver
applications
Pin out compatible with 74F74
74F50728 for synchronizing cascaded D–type flip–flop
See 74F50729 for synchronizing dual D–type flip–flop with
edge–triggered set and reset
See 74F50109 for synchronizing dual J–K positive
edge–triggered flip–flop
Industrial temperature range available (–40
°
C to +85
°
C)
TYPE
TYPICAL f
max
TYPICAL SUPPLY
CURRENT (TOTAL)
74F5074
120MHz
20mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F5074N
PKG DWG #
14–pin plastic DIP
SOT27-1
14–pin plastic SO
N74F5074D
SOT108-1
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
PINS
DESCRIPTION
74F
(U.L.)
HIGH/
LOW
LOAD VAL-
UE HIGH/
LOW
D0, D1
Data inputs
1.0/0.417
20
μ
A/250
μ
A
CP0, CP1
Clock inputs (active
rising edge)
1.0/1.0
20
μ
A/20
μ
A
SD0, SD1
Set inputs (active low)
1.0/1.0
20
μ
A/20
μ
A
RD0, RD1
Reset inputs (active
low)
1.0/1.0
20
μ
A/20
μ
A
Q0, Q1, Q0,
Q1
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the high
state and 0.6mA in the low state.
Data outputs
750/33
15mA/20mA
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
SD1
Q1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
Q0
SD0
SF00582
IEC/IEEE SYMBOL
D1
D0
Q0 Q0 Q1 Q1
5
6
9
8
2
12
V
= Pin 14
GND = Pin 7
CP0
SD0
RD0
CP1
SD1
RD1
3
4
1
11
10
13
SF00583
LOGIC SYMBOL
4
3
2
1
10
11
12
13
3
6
9
8
&
S
S
C1
C2
1D
2D
R
R
SF00584
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相關(guān)代理商/技術(shù)參數(shù) |
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