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參數(shù)資料
| 型號： | 74F433 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | First-In First-Out (FIFO) Buffer Memory |
| 中文描述： | 先入先出（FIFO）的緩沖存儲(chǔ)器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 166K |
| 代理商： | 74F433 |
3
www.fairchildsemi.com
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Functional Description
As shown in the block diagram, the 74F433 consists of
three sections:
1. An Input Register with parallel and serial data inputs,
as well as control inputs and outputs for input hand-
shaking and expansion.
2. A 4-bit-wide, 62-word-deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data out-
puts, as well as control inputs and outputs for output
handshaking and expansion.
These three sections operate asynchronously and are vir-
tually independent of one another.
Input Register (Data Entry)
The Input Register can receive data in either bit-serial or 4-
bit parallel form. It stores this data until it is sent to the fall-
through stack, and also generates the necessary status
and control signals.
This 5-bit register (see Figure 1) is initialized by setting flip-
flop F
3
and resetting the other flip-flops. The Q-output of
the last flip-flop (FC) is brought out as the Input Register
Full (IRF) signal. After initialization, this output is HIGH.
Parallel Entry
—A HIGH on the Parallel Load (PL) input
loads the D
0
–D
3
inputs into the F
0
–F
3
flip-flops and sets
the FC flip-flop. This forces the IRF output LOW, indicating
that the input register is full. During parallel entry, the Serial
Input Clock (CPSI) input must be LOW.
Serial Entry
—Data on the Serial Data (D
S
) input is serially
entered into the shift register (F
3
, F
2
, F
1
, F
0
, FC) on each
HIGH-to-LOW transition of the CPSI input when the Serial
Input Enable (IES) signal is LOW. During serial entry, the
PL input should be LOW.
After the fourth clock transition, the four data bits are
located in flip-flops F
0
–F
3
. The FC flip-flop is set, forcing
the IRF output LOW and internally inhibiting CPSI pulses
from affecting the register. Figure 2 illustrates the final posi-
tions in an 74F433 resulting from a 256-bit serial bit train
(B
0
is the first bit, B
255
the last).
FIGURE 1. Conceptual Input Section
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F433SPC | First-In First-Out (FIFO) Buffer Memory |
| 74F433DC | Multi-Mode FIFO |
| 74F433SPCQR | Multi-Mode FIFO |
| 74F538 | 1-of-8 Decoder with 3-STATE Outputs |
| 74F538SC | 1-of-8 Decoder with 3-STATE Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F433 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F433DC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Multi-Mode FIFO |
| 74F433SPC | 功能描述:寄存器 64x4 FIFO Buffer Mem RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74F433SPCQR | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Multi-Mode FIFO |
| 74F455 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Buffers/drivers |
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