- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375071 > 74F403 (Fairchild Semiconductor Corporation) First-In First-Out (FIFO) Buffer Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | 74F403 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | First-In First-Out (FIFO) Buffer Memory |
| 中文描述： | 先入先出（FIFO）的緩沖存儲(chǔ)器 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大小： | 167K |
| 代理商： | 74F403 |
3
www.fairchildsemi.com
7
FIGURE 1. Conceptual Input Section
FIGURE 2. Final Positions in a 74F403A
Resulting from a 64-Bit Serial Train
Transfer to the Stack—
The outputs of Flip-Flops F
0
-F
3
feed the stack. A LOW level on the TTS input initiates a
“fall-through” action. If the top location of the stack is
empty, data is loaded into the stack and the input register is
re-initialized. Note that this initialization is postponed until
PL is LOW again. Thus, automatic FIFO action is achieved
by connecting the IRF output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown
in Figure 10) in the control section records the fact that
data has been transferred to the stack. This prevents multi-
ple entry of the same word into the stack despite the fact
the IRF and TTS may still be LOW. The Request Initializa-
tion Flip-Flop is not cleared until PL goes LOW. Once in the
stack, data falls through the stack automatically, pausing
only when it is necessary to wait for an empty next location.
In the 74F403A as in most modern FIFO designs, the MR
input only initializes the stack control section and does not
clear the data.
OUTPUT REGISTER (DATA EXTRACTION)
The Output Register receives 4-bit data words from the
bottom stack location, stores it and outputs data on a 3-
STATE 4-bit parallel data bus or on a 3-STATE serial data
bus. The output section generates and receives the neces-
sary status and control signals. Figure 3 is a conceptual
logic diagram of the output section.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F403A | First-In First-Out (FIFO) Buffer Memory |
| 74F403ASPC | First-In First-Out (FIFO) Buffer Memory |
| 74F433 | First-In First-Out (FIFO) Buffer Memory |
| 74F433SPC | First-In First-Out (FIFO) Buffer Memory |
| 74F433DC | Multi-Mode FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F403A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:First-In First-Out (FIFO) Buffer Memory |
| 74F403A WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F403ASPC | 功能描述:寄存器 FIFO Buffer Memory RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74F403DC | 制造商:Freescale Semiconductor 功能描述: |
| 74F403SPC | 制造商:Rochester Electronics LLC 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。