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參數(shù)資料
| 型號(hào)： | 74F174 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Hex D-Type Flip-Flop with Master Reset |
| 中文描述： | 六角D類觸發(fā)器與主復(fù)位拖鞋 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 75K |
| 代理商： | 74F174 |
Philips Semiconductors
Product specification
74F174
Hex D flip-flop
October 7, 1988
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
TYP
2
UNIT
MIN
MAX
V
OH
High level output voltage
High-level output voltage
V
CC
= MIN, V
IL
= MAX
±
10%V
CC
2.5
V
V
IH
= MIN, I
OH
= MAX
±
5%V
CC
2.7
3.4
V
OL
Low level output voltage
Low-level output voltage
V
CC
= MIN, V
IL
= MAX
±
10%V
CC
0.30
0.50
V
V
IH
= MIN, I
OL
= MAX
±
5%V
CC
0.30
0.50
V
IK
I
I
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
–0.73
–1.2
V
Input current at maximum input voltage
100
μ
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
μ
A
I
IL
Low-level input current
V
CC
= MAX, V
I
= 0.5V
–0.6
mA
I
OS
Short-circuit output current
3
V
CC
= MAX
–60
–150
mA
I
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
= 5V, T
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
Supply current (total)
V
CC
= MAX, Dn = MR = 4.5V, CP =
↑
35
45
mA
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
f
MAX
Maximum clock frequency
Waveform 1
80
100
80
MHz
t
PLH
t
PHL
Propagation delay
CP to Qn
Waveform 1
3.5
4.5
5.5
6.0
8.0
10.0
3.5
4.5
9.0
11.0
ns
t
PHL
Propagation delay MR to Qn
Waveform 2
5.0
8.5
14.0
5.0
15.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
S
(H)
t
S
(L)
Setup time, High or Low
Dn to CP
Waveform 3
4.0
4.0
4.0
4.0
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Dn to CP
Waveform 3
0.0
0.0
0.0
0.0
ns
t
w
(H)
t
w
(L)
CP Pulse width,
High or Low
Waveform 1
4.0
6.0
4.0
6.0
ns
t
w
(L)
MR Pulse width, Low
Waveform 2
5.0
5.0
ns
t
REC
Recovery time, MR to CP
Waveform 2
5.0
5.0
ns
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