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參數(shù)資料
| 型號(hào)： | 74F1604 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Latch |
| 中文描述： | 鎖存 |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | 74F1604 |
Philips Semiconductors
Product specification
74F1604
Latch
2
October 4, 1990
853 0088 00619
FEATURES
High impedance NPN base inputs for reduced loading
(20
μ
A in high and low state)
Stores 16–bit wide data inputs, multiplexed 8–bit outputs
Propagation delay 7.0ns typical
Power supply current 70mA typical
DESCRIPTION
The 74F1604 is a dual octal transparent latch. Organized as 8–bit A
and B latches, the latch outputs are connected by pairs to eight
2–input multiplexers. A select (SELECT A/B) input determines
whether the A or B latch contents are multiplexed to the eight
outputs. Data from the B inputs are selected when SELECT A/B is
low; data from the A inputs are selected when SELECT A/B is high.
Data enters the latch on the falling edge of the latch enable (LE)
input. The latch remains transparent to the data inputs while LE is
low, and stores the data that is present one setup time before the
low–to–high latch enable transition.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY
CURRENT (TOTAL)
74F1604
7.0ns
70mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
PKG DWG #
28–pin plastic DIP
N74F1604N
SOT117-2
28–pin plastic SOL
N74F1604D
SOT136-1
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A7
Data inputs
1.0/0.033
20
μ
A/20
μ
A
B0 – B7
Data inputs
1.0/0.033
20
μ
A/20
μ
A
SELECT
A/B
Select input
1.0/0.033
20
μ
A/20
μ
A
LE
Latch enable input
(active low)
1.0/0.033
20
μ
A/20
μ
A
Q0 – Q7
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20
μ
A in the high state and
0.6mA in the low state.
Data outputs
50/33
1.0mA/20mA
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
19
20
21
22
23
24
25
26
27
28 V
CC
11
12
13
14
15
16
17
18
LE
SELECT A/B
A0
B0
A1
B1
A2
B2
A3
B3
Q3
Q2
Q1
GND
A4
B4
A5
B5
A6
B6
A7
B7
Q7
Q6
Q5
Q4
Q
SF00553
LOGIC SYMBOL
1
2
LE
SELCT A/B
A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6B6A7 B7
3 4 5
6
7
8
9 10 27 26 25 24 2322 21 20
15 13 12 11 16 17 18 19
Q0Q1Q2Q3Q4Q5Q6Q7
V
= Pin 28
GND = Pin 14
SF00554
IEC/IEEE SYMBOL
3
4
5
6
7
8
9
10
27
26
25
24
23
22
21
20
1
G2
C1
1D 2
1D 2
2
1
15
13
12
11
16
17
18
19
SF00555
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