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參數(shù)資料
| 型號： | 74F113 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual JK Negative Edge-Triggered Flip-Flop |
| 中文描述： | 雙JK負(fù)邊沿觸發(fā)器 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 74F113 |
Philips Semiconductors
Product specification
74F113
Dual J-K negative edge-triggered flip-flops
without reset
2
1996 Mar 14
853–0339 16575
FEATURE
Industrial temperature range available (–40
°
C to +85
°
C)
DESCRIPTION
The 74F113, dual negative edge-triggered JK-type flip-flop, features
individual J, K, clock (CP), set (SD) inputs, true and complementary
outputs. The asynchronous SD input, when low, forces the outputs
to the steady state levels as shown in the function table regardless
of the level at the other inputs.
A high level on the clock (CP) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CP is high and flip-flop will perform
according to the function table as long as minimum setup and hold
times are observed. Output changes are initiated by the high-to-low
transition of the CP.
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
SD1
Q1
Q1
J1
CP1
K1
CP0
K0
Q0
J0
SD0
Q0
SF00140
TYPE
TYPICAL f
max
100MHz
TYPICAL SUPPLY CURRENT (TOTAL)
74F113
15mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
INDUSTRIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= –40
°
C to +85
°
C
PKG. DWG. #
14-pin plastic DIP
N74F113N
I74F113N
SOT27–1
N74F113D
I74F113D
SOT108–1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
J0, J1
J inputs
1.0/1.0
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/2.4mA
20
μ
A/3.0mA
K0, K1
K inputs
1.0/1.0
CP0, CP1
Clock inputs (active falling edge)
1.0/4.0
SD0, SD1
Set inputs (active low)
1.0/5.0
Q0, Q1, Q0, Q1
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
Data outputs
50/33
1.0mA/20mA
LOGIC SYMBOL
Q0
Q0
Q1
Q1
5
6
9
8
V
= Pin 14
GND = Pin 7
1
4
13
10
CP0
SD0
CP1
SD1
J1
K0
2
12
SF00141
K1
J0
3
11
IEC/IEEE SYMBOL
3
1
2
4
11
13
12
10
5
6
9
8
1J
2J
C1
C2
1S
1K
2K
2S
SF00142
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F113PC | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F113SC | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F113SJ | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F11DC | Triple 3-input AND Gate |
| 54F11FMQB | Triple 3-input AND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F113 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F113PC | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74F113SC | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74F113SCX | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74F113SJ | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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