參數(shù)資料
型號(hào): 74F113
廠商: NXP Semiconductors N.V.
英文描述: Dual J-K negative edge-triggered flip-flops without reset
中文描述: 雙JK負(fù)邊沿觸發(fā)無復(fù)位觸發(fā)器
文件頁數(shù): 4/10頁
文件大?。?/td> 81K
代理商: 74F113
Philips Semiconductors
Product specification
74F113
Dual J-K negative edge-triggered flip-flops
without reset
1996 Mar 14
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
TYP
2
UNIT
MIN
MAX
V
OH
High level output voltage
High-level output voltage
= MIN, V
= MAX,
V
CC
MIN, V
IL
MAX,
V
IH
= MIN
= MAX
I
OH
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
V
2.7
3.4
V
V
OL
Low level output voltage
Low-level output voltage
= MIN, V
= MAX,
V
CC
MIN, V
IL
MAX,
V
IH
= MIN
= MAX
I
OL
0.30
0.50
V
0.30
0.50
V
V
IK
I
I
I
IH
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
–0.73
–1.2
V
μ
A
μ
A
mA
Input current at maximum input voltage
100
High-level input current
20
Jn, Kn
–0.6
I
IL
Low-level input current
CPn
V
CC
= MAX, V
I
= 0.5V
–2.4
mA
SDn
–3.0
mA
I
OS
I
CC
Short-circuit output current
3
Supply current
4
(total)
V
CC
= MAX
V
CC
= MAX
-60
–150
mA
15
21
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Measure I
CC
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
°
C
C
L
= 50pF
R
L
= 500
MIN
TYP
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF
R
L
= 500
MIN
V
CC
= +5.0V
±
10%
T
amb
= –40
°
C to +85
°
C
C
L
= 50pF
R
L
= 500
MIN
UNIT
MAX
MAX
MAX
f
max
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Waveform 1
85
100
80
80
ns
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn, to Qn or Qn
Waveform 1
2.0
2.0
2.0
2.0
4.0
4.0
4.5
4.5
6.0
6.0
6.5
6.5
2.0
2.0
2.0
2.0
7.0
7.0
7.5
7.5
2.0
2.0
2.0
2.0
7.5
7.0
8.0
7.5
ns
Waveform 2
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
°
C
L
= 50pF
R
L
= 500
MIN
TYP
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF
R
L
= 500
MIN
V
CC
= +5.0V
±
10%
T
amb
= –40
°
C to +85
°
C
C
L
= 50pF
R
L
= 500
MIN
UNIT
MAX
MAX
MAX
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
Setup time, high or low
Jn, Kn to CPn
Hold time, high or low
Jn, Kn to CPn
CP pulse width,
high or low
SDn pulse width, low
Waveform 1
4.0
3.5
0.0
0.0
4.5
4.5
4.5
5.0
4.0
0.0
0.0
5.0
5.0
5.0
5.0
4.5
0.0
0.0
5.0
5.0
5.0
ns
Waveform 1
ns
Waveform 1
ns
Waveform 2
ns
t
rec
Recovery time
SDn to CPn
Waveform 2
4.5
5.0
5.0
ns
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