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參數(shù)資料
| 型號(hào)： | 74F112 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual J-K negative edge-triggered flip-flop |
| 中文描述： | 雙JK負(fù)邊沿觸發(fā)器 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 83K |
| 代理商： | 74F112 |
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
February 9, 1990
3
LOGIC SYMBOL
Q0 Q0 Q1 Q1
5
6
9
7
V
= Pin 16
GND = Pin 8
1
4
15
13
10
14
CP0
SD0
RD0
CP1
SD1
RD1
J1
K0
2 12
SF00104
K1
J0
3
11
IEC/IEEE SYMBOL
SF00105
6
3
1
2
15
4
11
13
12
14
10
5
9
7
1J
C1
1K
R
S
2J
C2
2K
R
S
LOGIC DIAGRAM
5, 9
4, 10
2, 12
1, 13
6, 7
15, 14
3, 11
Qn
SDn
Kn
Qn
RDn
Jn
CPn
SF00106
V
= Pin 16
GND = Pin 8
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD
RD
CP
J
K
Q
Q
L
H
X
X
X
H
L
Asynchronous Set
H
L
X
X
X
L
H
Asynchronous Reset
L
L
X
X
X
H*
H*
Undetermined *
H
H
↓
h
h
q
q
Toggle
H
H
↓
l
h
L
H
Load “0” (Reset)
H
H
↓
h
l
H
L
Load “1” (Set)
H
H
↓
l
l
q
q
Hold “no change”
H
H
H
X
X
Q
Q
Hold “no change”
H = High voltage level
h = High voltage level one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don’t care
↓
= High-to-Low clock transition
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F112 | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F112PC | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F112SC | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F112SJ | Dual JK Negative Edge-Triggered Flip-Flop |
| 74F113 | Dual J-K negative edge-triggered flip-flops without reset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F112_00 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual JK Negative Edge-Triggered Flip-Flop |
| 74F112DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| 74F112N | 制造商:SNT 功能描述: |
| 74F112PC | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74F112PC | 制造商:Fairchild Semiconductor Corporation 功能描述:IC 74F FAST TTL LOGIC |
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