參數(shù)資料
型號： 74F109SJ
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Dual JK Positive Edge-Triggered Flip-Flop
中文描述： F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封裝： 0.300 INCH, EIAJ, SOIC-16
文件頁數(shù)： 4/10頁
文件大?。?/td> 85K
代理商： 74F109SJ
Philips Semiconductors
Product specification
74F109
Postive J-K positive edge-triggered flip-flops
October 23, 1990
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
TYP
2
UNIT
MIN
MAX
V
OH
High level output voltage
High-level output voltage
= MIN, V
= MAX,
V
CC
MIN, V
IL
MAX,
V
IH
= MIN
= MAX
I
OH
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
V
2.7
3.4
V
V
OL
Low level output voltage
Low-level output voltage
= MIN, V
= MAX,
V
CC
MIN, V
IL
MAX,
V
IH
= MIN
I
OL
= MAX
0.30
0.50
V
0.30
0.50
V
V
IK
I
I
I
IH
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
–0.73
–1.2
V
μ
A
μ
A
mA
Input current at maximum input voltage
100
High-level input current
20
I
IL
Low level input current
Low-level input current
J, K, CPn
–0.6
SDn, RDn
–1.8
mA
I
OS
I
CC
Short-circuit output current
3
Supply current
4
(total)
-60
–150
mA
12.3
17
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Measure I
CC
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
°
C
C
L
= 50pF
R
L
= 500
MIN
TYP
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF
R
L
= 500
MIN
V
CC
= +5.0V
±
10%
T
amb
= –40
°
C to +85
°
C
C
L
= 50pF
R
L
= 500
MIN
UNIT
MAX
MAX
MAX
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Waveform 1
90
125
90
90
MHz
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn, RD to Qn or Qn
Waveform 1
3.8
4.4
3.2
3.5
5.3
6.2
5.2
7.0
7.0
8.0
7.0
9.0
3.8
4.4
3.2
3.5
8.0
9.2
8.0
10.5
3.8
4.4
2.8
3.5
9.0
9.2
9.0
10.5
ns
Waveform 2, 3
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25
°
C
L
= 50pF
R
L
= 500
MIN
TYP
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF
R
L
= 500
MIN
V
CC
= +5.0V
±
10%
T
amb
= –40
°
C to +85
°
C
C
L
= 50pF
R
L
= 500
MIN
UNIT
MAX
MAX
MAX
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
Setup time, high or low
Dn to CPn
Waveform 1
3.0
3.0
3.0
3.0
3.0
3.0
ns
Hold time, high or low
Dn to CPn
Waveform 1
1.0
1.0
1.0
1.0
1.0
1.0
ns
CP pulse width,
high or low
SDn or RDn pulse width,
low
Recovery time
SDn or RDn to CP
Waveform 1
4.0
5.0
4.0
4.0
5.0
4.0
4.0
5.0
4.0
ns
Waveform 2
ns
t
rec
Waveform 3
2.0
2.0
2.0
ns
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