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| 型號(hào)： | 74B305 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | 74B305 |
TL/F/11750
C
July 1996
CGS74B304 Octal Divide-by-2 Skew Clock Driver
General Description
These minimum skew clock drivers are designed for high
frequency Clock Generation & Support (CGS) applications.
These devices are ideal for duty cycle recovery applications
with internal frequency divide-by-2 circuitry. The devices
guarantee minimum skew across the outputs of a given de-
vice. Skew parameters are also provided as a means to
measure duty cycle requirements as those found in high
speed clocking systems.
Functional Description
The CGS74B304 contains eight flip-flops designed to have
low skew between outputs. The eight outputs (eight in-
phase with CLK) toggle on successive CLK pulses.
PRE and CLR inputs are provided to set Q and Q outputs
high or low independent of CLK pin.
Features
Y
Clock Generation & Support (CGS) devices ideal for
high frequency signal generation or clock distribution
applications
Y
Fabricated on National’s Advanced Bipolar FAST
TM
LSl
process
Y
900 ps pin-to-pin output skew
Y
Specification for transition skew to meet duty cycle re-
quirements
Y
Current sourcing 24 mA and current sinking of 48 mA
Y
Low dynamic power consumption above 20 MHz
Y
Guaranteed 4 kV ESD protection
Logic Diagram
TL/F/11750–3
Connection Diagram
Pin Assignment
SOIC (M)
TL/F/11750–1
Pin Description
Pin Names
Description
CLK
Q
0
–Q
7
PRE
CLR
Clock Input
Outputs
Preset
Clear
Truth Table
Inputs
Outputs
CLR
PRE
CLK
Q
0
–Q
7
L
H
L
H
H
H
L
L
H
H
X
X
X
u
L
L
H
L
*
Q
0
Q
0
*
This state will not persist when CLR/PRE returns to high.
FAST
TM
is a trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
RRD-B30M86/Printed in U. S. A.
http://www.national.com
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