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參數(shù)資料
| 型號： | 74ALVCH16901PAG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO64 |
| 封裝： | GREEN, TSSOP-64 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 74ALVCH16901PAG |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
1
March 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-4582/3
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
IDT74ALVCH16901
3.3V CMOS 18-BIT
UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/
CHECKERS AND BUS-HOLD
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity
transceiver with registers. The device can operate as a feed-through
transceiver or it can generate/check parity from the two 8-bit data buses in
either direction.
The ALVCH16901 features independent clock (CLKAB or CLKBA),
latch-enable (LEAB or LEBA), and dual 9-bit clock enable (
CLKENAB or
CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/
EVEN) inputs and separate error-signal (ERRA and ERRB) outputs
for checking parity. The direction of data flow is controlled by
OEAB and
OEBA. When SELislow,theparityfunctionsareenabled. When SELishigh,
the parity functions are disabled and the device acts as an 18-bit registered
transceiver.
The ALVCH16901 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16901 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
1
CLKENAB
2
CLKENAB
LEAB
OEAB
ODD/EVEN
1
A1-1A8
SEL
B-Port
Parity
Generate
and
Check
A Data
2
A-Port
Parity
Generate
and
Check
B Data
18-Bit
Storage
CLKAB
1
APAR
1
ERRB
2
A1-2A8
2
APAR
2
ERRB
1
B1-1B8
1
BPAR
1
ERRA
2
B1-2A8
2
BPAR
2
ERRA
OEBA
CLKBA
1
CLKENBA
2
CLKENBA
LEBA
18-Bit
Storage
18
QA
QB
2
1
32
3
30
5
61
28
36
34
31
63
64
33
62
29
37
35
60
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVCH16903A4PA | 制造商:Integrated Device Technology Inc 功能描述: |
| 74ALVCH16903DGGRE4 | 功能描述:通用總線函數(shù) 3.3V 12B Univ Bus Dr RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH16903DGGRG4 | 功能描述:通用總線函數(shù) 3.3V 12B Univ Bus Dr RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH16903DGVRE4 | 功能描述:總線收發(fā)器 3.3V 12B Univ Bus Dr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVCH16903DGVRG4 | 功能描述:總線收發(fā)器 3.3V 12B Univ Bus Dr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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