參數(shù)資料
型號(hào): 74ALVCH162240TX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quad 4-Bit Buffer/Driver
中文描述: ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48
封裝: 6.10 MM, MO-153, TSSOP-48
文件頁數(shù): 1/6頁
文件大小: 86K
代理商: 74ALVCH162240TX
2001 Fairchild Semiconductor Corporation
DS500700
www.fairchildsemi.com
November 2001
Revised November 2001
7
74ALVCH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with Bushold and 26
Series Resistors in Outputs
General Description
The ALVCH162240 contains sixteen inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162240 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH162240 is also designed with 26
series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162240 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output capability up to 3.6V.
The 74ALVCH162240 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
I
1.65V to 3.6V V
CC
supply operation
I
3.6V tolerant control inputs and outputs
I
Bushold on data inputs eliminating the need for external
pull-up/pull-down resistors
I
26
series resistors in outputs
I
t
PD
3.8 ns max for 3.0V to 3.6V V
CC
4.3 ns max for 2.3V to 2.7V V
CC
7.6 ns max for 1.65V to 1.95V V
CC
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
74ALVCH162240T
Package Number
MTD48
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
I
0
I
15
O
0
O
15
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
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