參數(shù)資料
型號(hào)： 74ALVCF162835
廠商： Fairchild Semiconductor Corporation
英文描述： Quadruple Bus Buffer Gates With 3-State Outputs 14-SSOP -40 to 85
中文描述： 低電壓18位通用總線輸出為3.6V的容錯(cuò)和26з電阻的輸出驅(qū)動(dòng)器系列
文件頁(yè)數(shù)： 1/7頁(yè)
文件大小： 106K
代理商： 74ALVCF162835
2001 Fairchild Semiconductor Corporation
DS500668
www.fairchildsemi.com
September 2001
Revised October 2001
7
O
74ALVCF162835
Low Voltage 18-Bit Universal Bus Driver with 3.6V
Tolerant Outputs and 26
Series Resistors in Outputs
General Description
The 74ALVCF162835 low voltage 18-bit universal bus
driver combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Outputs (O
n
) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74ALVCF162835 is designed with 26
series resistors
in the outputs. This design reduces noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
The 74ALVCF162835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVCF162835 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
I
Compatible with PC133 DIMM module specifications
I
1.65V-3.6V V
CC
specifications provided
I
3.6V tolerant outputs
I
26
series resistors in outputs
I
t
PD
(CLK to O
n
)
3.7 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
7.4 ns max for 1.65V to 1.95V V
CC
I
Power-down high impedance outputs
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package
Number
MTD56
Package Description
74ALVCF162835T
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74ALVCF162835APA 功能描述:通用總線函數(shù) RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ALVCF162835APA8 功能描述:通用總線函數(shù) RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ALVCF162835APAG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
74ALVCF162835APAG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
74ALVCF162835APFG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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