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參數(shù)資料
| 型號(hào)： | 74ALVC16835MTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs |
| 中文描述： | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大小： | 88K |
| 代理商： | 74ALVC16835MTD |
www.fairchildsemi.com
4
7
AC Electrical Characteristics
AC Electrical Characteristics Over Load
(Note 7)
Note 7:
This parameter is guaranteed by characterization but not tested.
Capacitance
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C, R
L
=
500
C
L
=
50 pF
V
CC
=
3.3V
±
0.3V
V
CC
=
2.7V
Min
Max
Min
150
3.3
3.3
3.3
3.3
Units
C
L
=
30 pF
V
CC
=
2.5V
±
0.2V
Min
V
CC
=
1.8V
±
0.15V
Min
Max
150
Max
150
Max
100
f
CLOCK
t
W
Clock Frequency
Pulse Width LE High
MHz
3.3
3.3
4.0
4.0
ns
CLK High or Low
Data Before CLK
↑
Data Before LE
↓
CLK High
t
S
Setup Time
1.7
1.5
1.0
2.1
1.6
1.1
2.2
1.9
1.3
2.5
ns
CLK Low
t
H
Hold Time
Data After CLK
↑
Data After LE
↓
0.7
0.6
0.6
1.0
ns
CLK High
or Low
1.4
1.7
1.4
f
MAX
t
PHL
, t
PLH
Propagation Delay
Maximum Clock Frequency
150
1
1.3
150
150
1.0
1.3
100
1.5
1.5
MHz
I to O
LE to O
3.6
4.2
4.2
4.9
4.2
5.0
8.4
9.8
ns
CLK to O
1.4
1.1
1.3
4.5
4.6
3.9
5.2
5.6
4.3
1.4
1.4
1.0
5.5
5.5
4.5
2
9.2
9.8
7.6
t
PZL
, t
PZH
Output Enable Time
t
PLZ
, t
PHZ
Output Disable Time
1.5
1.5
ns
ns
Symbol
Parameter
R
L
=
500
, V
CC
=
3.3
±
0.15V
T
A
=
0
°
C to
+
85
°
C
C
L
=
0 pF
Min
Max
0.9
2.0
1.5
2.9
Units
T
A
=
0
°
C to
+
65
°
C
C
L
=
50 pF
Min
1.0
1.7
Max
4.0
4.5
t
PHL
, t
PLH
t
PHL
, t
PLH
Propagation Delay Bus to Bus
Propagation Delay Clock to Bus
ns
ns
Symbol
Parameter
Conditions
T
A
=
+
25
°
C
V
CC
3.3
Units
Typical
3
C
IN
Input Capacitance
Control
V
I
=
0V or V
CC
V
I
=
0V or V
CC
V
I
=
0V or V
CC
pF
Data
3.3
3.3
3.3
6
7
31
C
OUT
C
PD
Output Capacitance
Power Dissipation Capacitance
pF
Outputs Enabled f
=
10 MHz, C
L
=
0 pF
pF
2.5
3.3
2.5
26
14
12
Outputs Disabled f
=
10 MHz, C
L
=
0 pF
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