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參數(shù)資料
| 型號： | 74ALS112 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual J-K negative edge-triggered flip-flop |
| 中文描述： | 雙JK負邊沿觸發(fā)器 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 74ALS112 |
Philips Semiconductors
Product specification
74ALS112A
Dual J-K negative edge-triggered flip-flop
2
1996 Jun 27
853-1846 16995
DESCRIPTION
The 74ALS112A, dual negative edge-triggered JK-type flip-flop
features individual J, K, clock (CPn), set (SD), and reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the function table regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and the flip-flop will perform
according to the function table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
TYPE
TYPICAL
f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS112A
50MHz
3.0mA
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q1
V
CC
K1
J1
SD1
CP1
RD0
RD1
CP0
K0
Q0
J0
SD0
Q0
9
8
GND
Q1
SF00103
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
DRAWING
NUMBER
16-pin plastic DIP
74ALS112AN
SOT38-4
16-pin plastic SO
74ALS112AD
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
CP0, CP1
Clock Pulse input (active falling edge)
1.0/1.0
20
μ
A/0.1mA
J0, J1
J inputs
1.0/2.0
20
μ
A/0.2mA
K0, K1
K inputs
1.0/2.0
20
μ
A/0.2mA
SD0, SD1
Set inputs (active-Low)
1.0/2.0
20
μ
A/0.2mA
RD0, RD1
Reset inputs (active-Low)
1.0/2.0
20
μ
A/0.2mA
Q0, Q1, Q0, Q1
NOTE:
One (1.0) ALS unit load is defined as: 20
μ
A in the High state and 0.1mA in the Low state.
Data outputs
20/80
0.4mA/8mA
LOGIC SYMBOL
Q0 Q0 Q1 Q1
5
6
9
7
V
= Pin 16
GND = Pin 8
1
4
15
13
10
14
CP0
SD0
RD0
CP1
SD1
RD1
J1
K0
2 12
SF00104
K1
J0
3
11
IEC/IEEE SYMBOL
SF00105
6
3
1
2
15
4
11
13
12
14
10
5
9
7
1J
C1
1K
R
S
2J
C2
2K
R
S
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALS112A | Dual J-K negative edge-triggered flip-flop |
| 74ALS112AD | Dual J-K negative edge-triggered flip-flop |
| 74ALS112AN | Dual J-K negative edge-triggered flip-flop |
| 74ALS11AD | Triple 3-Input AND gate |
| 74ALS11A | Triple 3-Input AND gate(三3輸入與門) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALS112A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K negative edge-triggered flip-flop |
| 74ALS112AD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K negative edge-triggered flip-flop |
| 74ALS112AN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K negative edge-triggered flip-flop |
| 74ALS11A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-Input AND gate |
| 74ALS11AD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-Input AND gate |
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