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參數(shù)資料
| 型號(hào)： | 74ALS109A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual J-K positive edge-triggered flip-flop with set and reset |
| 中文描述： | 雙JK上升沿觸發(fā)器設(shè)置和復(fù)位觸發(fā)器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 93K |
| 代理商： | 74ALS109A |
Philips Semiconductors
Product specification
74ALS109A
Dual J-K positive edge triggered flip-flop
with set and reset
1991 Feb 08
5
AC WAVEFORMS
For all waveforms, V
M
= 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
M
V
M
CPn
V
M
V
M
V
M
V
M
V
M
V
M
t
su
(H)
t
h
(H)
Jn,
Kn
Qn
V
M
t
w
(H)
1/f
max
t
su
(L)
t
h
(L)
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SC00043
Waveform 1.
Data Setup Time and Hold Times, Clock Width,
and Maximum Clock Frequency
Propagation Delay for Data to Output,
V
M
CPn
Qn
V
M
V
M
Qn
t
PHL
t
PLH
SDn
V
M
V
M
t
w
(L)
SC00044
Jn, Kn
t
REC
Waveform 2.
Set Pulse Width and Recovery Time for Set to Clock
Propagation Delay for Set to Output,
V
M
CPn
Qn
V
M
V
M
Qn
t
PHL
t
PLH
RDn
V
M
V
M
t
w
(L)
SC00045
Jn, Kn
t
REC
Waveform 3.
Reset Pulse Width and Recovery Time for Reset to Clock
Propagation Delay for Reset to Output,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALS109AD | Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS109AN | Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS10A | Triple 3-Input NAND gate |
| 74ALS10AD | Triple 3-Input NAND gate |
| 74ALS10AN | Triple 3-Input NAND gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALS109AD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS109AN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS109ANNSC91 | 制造商:National Semiconductor 功能描述:74ALS109N |
| 74ALS10A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-Input NAND gate |
| 74ALS10AD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-Input NAND gate |
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