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參數(shù)資料
| 型號： | 74AHCT132PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad 2-input NAND Schmitt trigger |
| 中文描述： | AHCT/VHCT SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, SOT-402-1, TSSOP-14 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 106K |
| 代理商： | 74AHCT132PWDH |
1999 Sep 24
2
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74AHC132; 74AHCT132
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V;
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
Inputsacceptsvoltageshigherthan
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125
°
C.
DESCRIPTION
The 74AHC/AHCT132 are
high-speed Si-gate CMOS devices
and are pin compatible with Low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT132 contain four
2-input NAND gates which accept
standard input signals. They are
capable of transforming slowly
changing input signals into sharply
defined, jitter free output signals.
The gate switches at different points
for positive and negative-going
signals. The difference between the
positive voltage V
T+
and the negative
V
T
is defined as the hysteresis
voltage V
H
.
FUNCTION TABLE
See note 1.
Note
1.
H = HIGH voltage level; L = LOW voltage level.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
INPUTS
OUTPUT
nA
nB
nY
L
L
H
H
L
H
L
H
H
H
H
L
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nA to nY
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
3.3
3.5
ns
C
I
C
O
C
PD
3.0
4.0
11
3.0
4.0
14
pF
pF
pF
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PACKAGES
PINS
PACKAGE
MATERIAL
CODE
74AHC132D
74AHC132PW
74AHCT132D
74AHCT132PW
74AHC132D
74AHC132PW DH
74AHCT132D
74AHCT132PW DH
14
14
14
14
SO
plastic
plastic
plastic
plastic
SOT108-1
SOT402-1
SOT108-1
SOT402-1
TSSOP
SO
TSSOP
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