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參數(shù)資料
| 型號(hào)： | 74ACTQ543SC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 17-Bit LVTTL-to-GTLP Universal Bus Transceiver with Buffered Clock Outputs 56-TVSOP -40 to 85 |
| 中文描述： | ACT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 0.300 INCH, MS-013, SOIC-24 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 93K |
| 代理商： | 74ACTQ543SC |
www.fairchildsemi.com
2
7
Logic Symbols
IEEE/IEC
Functional Description
The ACQ/ACTQ543 contains two sets of eight D-type
latches, with separate input and output controls for each
set. For data flow from A to B, for example, the A-to-B
Enable (CEAB) input must be LOW in order to enter data
from A
0
–
A
7
or take data from B
0
–
B
7
, as indicated in the
Data I/O Control Table. With CEAB LOW, a LOW signal on
the A-to-B Latch Enable (LEAB) input makes the A-to-B
latches transparent; a subsequent LOW-to-HIGH transition
of the LEAB signal puts the A latches in the storage mode
and their outputs no longer change with the A inputs. With
CEAB and OEAB both LOW, the 3-STATE B output buffers
are active and reflect the data present at the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA inputs
Data I/O Control Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Latch Status
Output Buffers
CEAB
LEAB
OEAB
H
X
X
Latched
High Z
X
H
X
Latched
—
L
L
X
Transparent
—
X
X
H
—
High Z
L
X
L
—
Driving
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ACQ543SCX | CMOS, µP Compatible, 5µs/10µs, 8-Bit ADCs |
| 74ACTQ543QSCX | Single 8-bit Bus Transceiver |
| 74ACTQ543SCX | Single 8-bit Bus Transceiver |
| 74ACQ543SC | Quiet Series⑩ Octal Registered Transceiver with 3-STATE Outputs |
| 74ACTQ544 | 17-Bit LVTTL-to-GTLP Universal Bus Transceiver with Buffered Clock Outputs 56-TVSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ACTQ543SCX | 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ACTQ543SPC | 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ACTQ544 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74ACTQ544SC | 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ACTQ544SC_Q | 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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