- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375066 > 74ACTQ18823MTDX (FAIRCHILD SEMICONDUCTOR CORP) 18-Bit D-Type Flip-Flop PDF資料下載
參數(shù)資料
| 型號： | 74ACTQ18823MTDX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 18-Bit D-Type Flip-Flop |
| 中文描述： | ACT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 74ACTQ18823MTDX |
www.fairchildsemi.com
2
7
Connection Diagram
Functional Description
The ACTQ18823 consists of eighteen D-type edge-trig-
gered flip-flops. These have 3-STATE outputs for bus sys-
tems organized with inputs and outputs on opposite sides.
The device is byte controlled with each byte functioning
identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation. The
following description applies to each byte. The buffered
clock (CP
n
) and buffered Output Enable (OE
n
) are com-
mon to all flip-flops within that byte. The flip-flops will store
the state of their individual D inputs that meet set-up and
hold time requirements on the LOW-to-HIGH CP
n
transi-
tion. With OE
n
LOW, the contents of the flip-flops are avail-
able at the outputs. When OE
n
is HIGH, the outputs go to
the impedance state. Operation of the OE
n
input does not
affect the state of the flip-flops. In addition to the Clock and
Output Enable pins, there are Clear (CLR
n
) and Clock
Enable (EN
n
) pins. These devices are ideal for parity bus
interfacing in high performance systems.
When CLR
n
is LOW and OE
n
is LOW, the outputs are
LOW. When CLR
n
is HIGH, data can be entered into the
flip-flops. When EN
n
is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the EN
n
is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Function Table
(Note 1)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Note 1:
The table represents the logic for one byte. The two bytes are independent of each other and function identically.
Inputs
Internal
Output
Function
OE
CLR
EN
CP
I
n
Q
O
n
H
X
L
L
L
Z
High Z
H
X
L
H
H
Z
High Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
Clear
H
H
H
X
X
NC
Z
Hold
L
H
H
X
X
NC
NC
Hold
H
H
L
L
L
Z
Load
H
H
L
H
H
Z
Load
L
H
L
L
L
L
Load
L
H
L
H
H
H
Load
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ACTQ18823SSC | 18-Bit D-Type Flip-Flop with 3-STATE Outputs |
| 74ACTQ18825 | 18-Bit Buffer/Line Driver with 3-STATE Outputs |
| 74ACTQ18825MTD | 18-Bit Buffer/Line Driver with 3-STATE Outputs |
| 74ACTQ18825MTDX | 18-Bit Buffer/Driver |
| 74ACTQ18825SSCX | 18-Bit Buffer/Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ACTQ18823SSC | 功能描述:觸發(fā)器 18-Bit D Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ACTQ18823SSC_Q | 功能描述:觸發(fā)器 18-Bit D Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ACTQ18823SSCX | 功能描述:觸發(fā)器 18-Bit D Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ACTQ18825_ZAB3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74ACTQ18825_ZAB3116B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。