參數(shù)資料
型號(hào): 74ACTQ16543MTD
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 16-Bit Registered Transceiver with 3-STATE Outputs
中文描述: ACT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: 6.10 MM, MO-153, TSSOP-56
文件頁(yè)數(shù): 6/9頁(yè)
文件大?。?/td> 76K
代理商: 74ACTQ16543MTD
www.fairchildsemi.com
6
7
Extended AC Electrical Characteristics
Note 10:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high,
high-to-low, etc.).
Note 11:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12:
3-STATE delays are load dominated and have been excluded from the datasheet.
Note 13:
The Output Disable Time is dominated by the RC network (500
, 250 pF) on the output and has been excluded from the datasheet.
Note 14:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
OSHL
), LOW to HIGH (t
OSLH
), or any combination switching LOW to HIGH and/or HIGH to
LOW (t
OST
).
Capacitance
T
A
=
40 to
+
85
°
C
V
CC
=
Com
C
L
=
50 pF
16 Outputs Switching
(Note 10)
Typ
T
A
=
40 to
+
85
°
C
V
CC
=
Com
C
L
=
250 pF
(Note 11)
Min
5.8
Symbol
Parameter
Units
Min
4.5
Max
11.1
Max
14.3
t
PLH
t
PHL
Propagation Delay
Transparent Mode
A
n
to B
n
or B
n
to A
n
Propagation Delay
3.7
9.6
5.1
13.4
ns
t
PLH
t
PHL
t
PZH
t
PZL
4.3
11.3
6.2
16.3
ns
LEBA
n
, LEAB
n
to A
n
, B
n
Output Enable Time
3.7
9.7
5.8
14.9
4.0
10.7
OEBA
n
or OEAB
n
to A
n
or B
n
CEBA
n
or CEAB
n
to A
n
or B
n
Output Disable Time
4.3
11.3
(Note 12)
ns
t
PHZ
t
PLZ
3.0
8.0
OEBA
n
or OEAB
n
to A
n
or B
n
CEBA
n
or CEAB
n
to A
n
or B
n
Pin to Pin Skew
HL Data to Output
Pin to Pin Skew
2.8
7.6
(Note 13)
ns
t
OSHL
(Note 14)
t
OSLH
(Note 14)
t
OSHL
(Note 14)
1.1
ns
1.4
ns
LH Data to Output
Pin to Pin Skew
Latch to Output
2.6
ns
t
OSLH
(Note 14)
t
OST
(Note 14)
t
OST
(Note 14)
Pin to Pin Skew
Latch to Output
Pin to Pin Skew
1.0
ns
1.0
ns
Data to Output
Pin to Pin Skew
Latch to Output
2.2
ns
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
C
IN
C
PD
Input Capacitance
V
CC
=
5.0V
V
CC
=
5.0V
Power Dissipation.Capacitance
95.0
pF
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74ACTQ16543SSC 功能描述:總線收發(fā)器 16-Bit Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ACTQ16543SSC_Q 功能描述:總線收發(fā)器 16-Bit Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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