參數(shù)資料
型號: 74ACT353
廠商: Motorola, Inc.
英文描述: 18-Bit LVTTL To GTL/GTL+ Bus Transceiver 64-TSSOP -40 to 85
中文描述: 雙路4輸入多路復(fù)用器與三態(tài)輸出
文件頁數(shù): 2/8頁
文件大?。?/td> 179K
代理商: 74ACT353
MC74AC353 MC74ACT353
5-2
FACT DATA
FUNCTIONAL DESCRIPTION
The MC74AC353/74ACT353 contains two identical
4-input multiplexers with 3-state outputs. They select two bits
from four sources selected by common Select inputs (S0, S1).
The 4-input multiplexers have individual Output Enable (OEa,
OEb) inputs which, when HIGH, force the outputs to a high
impedance (High Z) state. The logic equations for the outputs
are shown below:
Za = OEa
(I0a
S1
S0+I1a
S1
S0+
I2a
S1
S0+I3a
S1
S0)
Zb = OEb
(I0b
S1
S0+I1b
S1
S0+
I2b
S1
S0+I3b
S1
S0)
If the outputs of 3-state devices are tied together, all but one
device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
OEb
I3b
I2b
I1b
I0b
S0
S1
I3a
I2a
Zb
Za
I1a
I0a
OEa
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
LOGIC DIAGRAM
相關(guān)PDF資料
PDF描述
74ACT521 8-BIT IDENTITY COMPARATOR
74ACT521 8-Bit Identity Comparator
74ACT521PC 8-Bit Identity Comparator
74ACT521SC 8-Bit Identity Comparator
74ACT521SJ 2-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Selectable Polarity 16-SOIC -40 to 85
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