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參數(shù)資料
| 型號： | 74ACT323 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Replaced by SN74GTLPH16612 : 18-Bit LVTTL-To-GTL/GTL+ Universal Bus Transceivers 56-TSSOP -40 to 85 |
| 中文描述： | 8位通用移位/存儲與同步復(fù)位和通用I / O引腳注冊 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 55K |
| 代理商： | 74ACT323 |
www.fairchildsemi.com
2
7
Functional Description
The ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0
and S
1
as shown
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Inputs
Response
SR
S
1
S
0
CP
L
X
X
Synchronous Reset; Q
0
–Q
7
=
LOW
Parallel Load; I/O
n
→
Q
n
Shift Right; DS
0
→
Q
0
, Q
0
→
Q
1
, etc.
Shift Left; DS
7
→
Q
7
, Q
7
→
Q
6
, etc.
Hold
H
H
H
H
L
H
H
H
L
H
L
L
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ACT373MTCX-NL | Octal Transparent Latch with 3-STATE Outputs |
| 74ACT373SCX-NL | Octal Transparent Latch with 3-STATE Outputs |
| 74ACT520SCX | Identity Comparator |
| 74AC520 | 8-Bit Identity Comparator |
| 74AC520PC | 8-Bit Identity Comparator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ACT323 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74ACT323PC | 功能描述:計數(shù)器移位寄存器 8-Bit Shift/Stor Reg RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74ACT323PC_Q | 功能描述:計數(shù)器移位寄存器 8-Bit Shift/Stor Reg RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74ACT32B | 功能描述:邏輯門 Quad 2-Input OR RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74ACT32M | 功能描述:邏輯門 RO 511-74ACT32M-TR RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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