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參數(shù)資料
| 型號(hào)： | 74ACT11853 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit to 9-Bit Parity Bus Transceiver(8位-9位奇偶總線收發(fā)器) |
| 中文描述： | 8位9位奇偶總線收發(fā)器（8位-9位奇偶總線收發(fā)器） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 82K |
| 代理商： | 74ACT11853 |
54ACT11853, 74ACT11853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
°
C
TYP
54ACT11853
MIN
74ACT11853
MIN
UNIT
MIN
MAX
0.5
MAX
MAX
IOH
ERR
VO = VCC
5.5 V
3 V
4.5 V
5.5 V
3 V
4.5 V
5.5 V
5.5 V
5.5 V
3 V
4.5 V
5.5 V
3 V
4.5 V
5.5 V
5.5 V
5.5 V
10
5
A
VOH
All outputs except
ERR
IOH = – 50 A
2.9
4.4
5.4
2.58
3.94
4.94
4.4
4.4
5.4
2.4
3.7
4.7
3.85
4.4
4.4
5.4
2.48
3.8
4.8
V
IOH = – 4 mA
IOH= – 24 mA
IOH = – 24 mA
IOH = – 50 mA
IOH = – 75 mA
3.85
VOL
IOL = 50 A
0.1
0.1
0.1
0.36
0.36
0.36
0.1
0.1
0.1
0.5
0.5
0.5
1.65
0.1
0.1
0.1
0.44
0.44
0.44
V
IOL = 12 mA
IOL= 24 mA
IOL = 24 mA
IOL = 50 mA
IOL = 75 mA
1.65
IOZ
A or B ports,
PARITY
OEA, OEB, LE,
and CLR
VO = VCC or GND
5.5 V
±
0.5
±
10
±
5
A
II
VI = VCC or GND
5.5 V
±
0.1
±
1
±
1
A
ICC
VI = VCC or GND, IO = 0
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
8
160
80
A
ICC
5.5 V
0.9
1
1
mA
Ci
OEA, OEB, LE,
and CLR
VI= VCCor GND
VI = VCC or GND
5 V
4 5
4.5
pF
Cio
A or B ports,
PARITY
VI = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended oepration free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Note 2)
TA = 25
°
C
MIN
5
5
5
14
2
0
54ACT11853
MIN
5
5
5
14
2
0
74ACT11853
MIN
5
5
5
14
2
0
UNIT
MAX
MAX
MAX
P l
Pulse duration
LE high
LE low
CLR low
Bi and PARITY
CLR inactive
tw
ns
tsu
Setup time before LE
Setup time, before LE
↓
ns
th
Hold time, Bi and PARITY after LE
↓
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of Advanced CMOS Logic Data Book 1990.
ns
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