參數(shù)資料
型號(hào): 74ACQ544SCX
廠(chǎng)商: FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi): 通用總線(xiàn)功能
英文描述: CMOS, µP Compatible, 5µs/10µs, 8-Bit ADCs
中文描述: AC SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24
封裝: 0.300 INCH, MS-013, SOIC-24
文件頁(yè)數(shù): 2/9頁(yè)
文件大?。?/td> 86K
代理商: 74ACQ544SCX
www.fairchildsemi.com
2
7
Logic Symbols
IEEE/IEC
Functional Description
The ACQ/ACTQ544 contains two sets of eight D-type
latches, with separate input and output controls for each
set. For data flow from A to B, for example, the A-to-B
Enable (CEAB) input must be LOW in order to enter data
from A
0
A
7
or take data from B
0
B
7
, as indicated in the
Data I/O Control Table. With CEAB LOW, a LOW signal on
the A-to-B Latch Enable (LEAB) input makes the A-to-B
latches transparent; a subsequent LOW-to-HIGH transition
of the LEAB signal puts the A latches in the storage mode
and their outputs no longer change with the A inputs. With
CEAB and OEAB both LOW, the 3-STATE B output buffers
are active and reflect the data present at the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA inputs.
Data I/O Control Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Latch
Output
CEAB
LEAB
OEAB
Status
Buffers
H
X
X
Latched
High Z
X
H
X
Latched
L
L
X
Transparent
X
X
H
High Z
L
X
L
Driving
相關(guān)PDF資料
PDF描述
74ACQ544SPC Single 8-Bit Inverting Bus Transceiver
74ACTQ544SC Single 8-Bit Inverting Bus Transceiver
74ACTQ544SCX Single 8-Bit Inverting Bus Transceiver
74ACTQ544SPC Single 8-Bit Inverting Bus Transceiver
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