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參數(shù)資料
| 型號(hào)： | 74AC373SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal Transparent Latch with 3-STATE Outputs |
| 中文描述： | AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 241K |
| 代理商： | 74AC373SJ |
74AC373
5/11
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
LE to Q
t
PLH
t
PHL
Propagation Delay
Time
D to Q
t
PZL
t
PZH
Output Enable
Time
3.3
(*)
5.0
(**)
6.5
12.0
14.0
14.0
ns
5.0
9.5
10.5
10.5
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
6.5
12.0
14.0
14.0
ns
5.0
9.5
10.5
10.5
7.0
11.0
13.0
13.0
ns
5.0
8.5
9.5
9.5
t
PLZ
t
PHZ
Output Disable
Time
7.5
12.0
13.0
13.0
ns
6.5
9.0
10.0
10.0
t
W
CLOCK Pulse
Width HIGH or
LOW
Setup Time D to
CLOCK, HIGH or
LOW
Hold Time D to
CLOCK, HIGH or
LOW
1.5
5.5
6.0
6.0
ns
1.5
4.0
4.5
4.5
t
s
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
0.5
5.5
6.0
6.0
ns
0.5
4.0
4.5
4.5
t
h
-0.5
1.0
5.0
5.0
ns
-0.5
1.0
5.0
5.0
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance (note
1)
5.0
4
pF
C
OUT
5.0
8
pF
C
PD
5.0
f
IN
= 10MHz
20
pF
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