參數(shù)資料
型號(hào): 74AC139SJX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 2-To-4-Line Demultiplexer
中文描述: AC SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
封裝: 5.30 MM, EIAJ TYPE2, SOIC-16
文件頁(yè)數(shù): 1/9頁(yè)
文件大?。?/td> 98K
代理商: 74AC139SJX
1999 Fairchild Semiconductor Corporation
DS009926
www.fairchildsemi.com
November 1988
Revised November 1999
7
74AC139
74ACT139
Dual 1-of-4 Decoder/Demultiplexer
General Description
The AC/ACT139 is a high-speed, dual 1-of-4 decoder/
demultiplexer. The device has two independent decoders,
each accepting two inputs and providing four mutually-
exclusive active-LOW outputs. Each decoder has an
active-LOW Enable input which can be used as a data
input for a 4-output demultiplexer. Each half of the AC/
ACT139 can be used as a function generator providing all
four minterms of two variables.
Features
I
I
CC
reduced by 50%
I
Multifunction capability
I
Two completely independent 1-of-4 decoders
I
Active LOW mutually exclusive outputs
I
Outputs source/sink 24 mA
I
ACT139 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
FACT
is a trademark of Fairchild Semiconductor Corporation.
Order Number
74AC139SC
74AC139SJ
74AC139MTC
74AC139PC
74ACT139SC
74ACT139SJ
74ACT139MTC
74ACT139PC
Package Number
M16A
M16D
MTC16
N16E
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150
Narrow Body
16-Lead Small Outline Package (SOIC), EIAJ Type II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300
Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150
Narrow Body
16-Lead Small Outline Package (SOIC), EIAJ Type II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300
Wide
Pin Names
Description
A
0
, A
1
E
Address Inputs
Enable Inputs
O
0
O
3
Outputs
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