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參數(shù)資料
| 型號： | 74AC11881 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Arithmetic Logic Units/Fuction Generators(算術(shù)邏輯單元/函數(shù)發(fā)生器) |
| 中文描述： | 算術(shù)邏輯單元/作用分析發(fā)生器（算術(shù)邏輯單元/函數(shù)發(fā)生器） |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 236K |
| 代理商： | 74AC11881 |
Cn
DATA INPUTS
Cn
DATA INPUTS
54AC11881, 74AC11881
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
description (continued)
In the logic mode, the
′
ACT11881 provides the user with a status check on the input words A and B and the output
word F. While in the logic mode, the P, G, and C
n + 4
outputs supply status information based upon the following
logical combinations:
P = F0 + F1 + F2 + F3
G = H
C
n + 4
= PC
n
.
Function Tables for Input Bits Equal/Not Equal
S0 = S3 = H, S1 = S2 = L, AND M = H
OUTPUTS
P
L
L
H
H
H
H
G
H
H
H
H
H
H
Cn+4
H
L
L
L
L
L
H
L
X
X
X
X
A0 = B0
A0 = B0
A0
≠
B0
X
X
X
A1 = B1
A1 = B1
X
A1
≠
B1
X
X
A2 = B2
A2 = B2
X
X
A2
≠
B2
X
A3 = B3
A3 = B3
X
X
X
A3
≠
B3
S0 = S1 = S3 = L, S2 = H, AND M = H
OUTPUTS
P
L
L
H
H
H
H
G
H
H
H
H
H
H
Cn+4
H
L
L
L
L
L
H
L
X
X
X
X
A0 or B0 = L
A0 or B0 = L
A0 = B0 = H
X
X
X
A1 or B1 = L
A1 or B1 = L
X
A1 = B1 = H
X
X
A2 or B2 = L
A2 or B2 = L
X
X
A2 = B2 = H
X
A3 or B3 = L
A3 or B3 = L
X
X
X
A3 = B3 = H
The combination of signals on the S3 through S0 control lines determine the operation performed on the data
words to generate the output bits Fi. By monitoring the P and C
n + 4
outputs, the user can determine if all pairs
of input bits are equal (see table above) or if any pair of inputs are both high (see table above). The
′
ACT11881
has the unique feature of providing an A = B status while the exclusive-OR (
⊕
) function is being utilized. When
the control inputs (S3, S2, S1, S0) equal H, L, L, H; a status check is generated to determine whether all pairs
(Ai, Bi) are equal in the following manner: P = (A0
⊕
B0) + (A1
⊕
B1) + (A2
⊕
B2) + (A3
⊕
B3). This unique
bit-by-bit comparison of the data words, which is available on the totem-pole P output, is particularly useful when
cascading
′
ACT11881s. As the A = B condition is sensed in the first stage, the signal is propagated through
the same ports used for carry generation in the arithmetic mode (P and G). Thus, the A = B status is transmitted
to the second stage more quickly without the need for external multiplexing logic. The A = B open-drain output
allows the user to check the validity of the bit-by-bit result by comparing the two signals for parity.
If the user wishes to check for any pair of data inputs (Ai, Bi) being high, it is necessary to set the control lines
(S3, S2, S1, S0) to L, H, L, L. The data pairs will then be ANDed together and the results ORed in the following
manner: P = A0B0 +A1B1 + A2B2 +A3B3.
S3
L
H
S2
H
L
S1
L
L
S0
L
H
M
H
H
P = F0 + F1 + F2 + F3
A0B0 + A1B1 + A2B2 + A3B3
(A0
⊕
B0) + (A1
⊕
B1) + (A2
⊕
B2) + (A3
⊕
B3)
P
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PDF描述 |
|---|---|
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| 74AC11PC | Triple 3-Input AND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
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| 74AC11898 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit serial-in parallel-out shift register |
| 74AC11898D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit serial-in parallel-out shift register |
| 74AC11898N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit serial-in parallel-out shift register |
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