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參數(shù)資料
| 型號： | 74ABT16833DGGRG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL 8-9BIT BUS TXRX 56-TSSOP |
| 標準包裝： | 2,000 |
| 系列： | 74ABT |
| 邏輯類型： | 收發(fā)器，非反相 |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 8 |
| 輸出電流高，低： | 32mA，64mA |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
SN54ABT16833, SN74ABT16833
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Members of the Texas Instruments
Widebus
Family
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes
PCB Layout
D High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D Parity-Error Flag With Parity
Generator/Checker
D Register for Storage of Parity-Error Flag
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16833 consist of two noninverting 8-bit
to 9-bit parity bus transceivers and are designed
for communication between data buses. For each
transceiver, when data is transmitted from the
A bus to the B bus, an odd-parity bit is generated
and output on the parity I/O pin (1PARITY or
2PARITY). When data is transmitted from the
B bus to the A bus, 1PARITY (or 2PARITY) is
configured as an input and combined with the
B-input data to generate an active-low error flag if
odd parity is not detected.
The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity-error flag is
clocked into 1ERR (or 2ERR) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR (or 2ERR)
is cleared (set high) by taking the clear (1CLR or 2CLR) input low.
The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively
isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity
is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic
capability.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright
1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Widebus and EPIC-
ΙΙB are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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1OEB
1CLK
1ERR
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2ERR
2CLK
2OEB
1OEA
1CLR
1PARITY
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2PARITY
2CLR
2OEA
SN54ABT16833 . . . WD PACKAGE
SN74ABT16833 . . . DGG OR DL PACKAGE
(TOP VIEW)
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