參數(shù)資料
型號(hào): 73S1215F-44IMR/F/P
廠商: Maxim Integrated Products
文件頁數(shù): 8/136頁
文件大?。?/td> 0K
描述: IC SMART CARD READER PROG 44-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART,USB
外圍設(shè)備: LED,POR,WDT
輸入/輸出數(shù): 9
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
DS_1215F_003
73S1215F Data Sheet
Rev. 1.4
105
CRC MS Value Registers (CRCMsB): 0xFE14
0xFF, (CRCLsB): 0xFE15
0xFF
Table 103: The CRCMsB Register
MSB
LSB
CRC.15
CRC.14
CRC.13
CRC.12
CRC.11
CRC.10
CRC.9
CRC.8
Table 104: The CRCLsB Register
MSB
LSB
CRC.7
CRC.6
CRC.5
CRC.4
CRC.3
CRC.2
CRC.1
CRC.0
The 16-bit CRC value forms the TX CRC word in TX mode (write value) and the RX CRC in RX mode
(read value). The initial value of CRC to be used when generating a CRC to be transmitted at the end of
a message (after the last TX byte is sent) when enabled in T=1 mode. Should be reloaded at the
beginning of every message to be transmitted. When using CRC, the both CRC registers should be
initialized to FF. When using LRC the CRCLsB Value register should be loaded to 00. When receiving a
message, the firmware should load this with the initial value and then read this register to get the final
value at the end of the message. These registers need to be reloaded for each new message to be
received. When in LRC mode, bits (7:0) are used and bits (15:8) are undefined. During LRC/CRC
checking and generation, this register is updated with the current value and can be read to aid in
debugging. This information will be transmitted to the smart card using the timing specified by the Guard
Time register. When checking CRC/LRC on an incoming message (CRC/LRC is checked against the
data and CRC/LRC), the firmware reads the final value after the message has been received and
determines if an error occurred (= 0x1D0F (CRC_ no error, else error; = 0 (LRC) no error, else error).
When a message is received, the CRC/LRC is stored in the FIFO. The polynomial used to generate and
check CRC is x
16 + x12+ x5 +1. When in indirect convention, the CRC is generated prior to the conversion
into indirect convention. When in indirect convention, the CRC is checked after the conversion out of
indirect convention. For a given message, the CRC generated (and readable from this register) will be
the same whether indirect or direct convention is used to transmit the data to the smart card. The
CRCLsB / CRCMsB registers will be updated with CRC/LRC whenever bits are being received or
transmitted from/to the smart card (even if CRCEN is not set and in mode T1). They are available to the
firmware to use if desired.
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