參數資料
型號: 73S1209F-44IM/F/P
廠商: Maxim Integrated Products
文件頁數: 119/123頁
文件大小: 0K
描述: IC SMART CARD READER PROG 44-QFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 260
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART
外圍設備: LED,POR,WDT
輸入/輸出數: 9
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 管件
DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
95
FD Control Register (FDReg): 0xFE13
0x11
Table 91: The FDReg Register
MSB
LSB
FVAL.3
FVAL.2
FVAL.1
FVAL.0
DVAL.3
DVAL.2
DVAL.1
DVAL.0
Bit
Symbol
Function
FDReg.7
FVAL.3
Refer to Table 93 above. This value is converted per the table to set the
divide ratio used to generate the baud rate (ETU). Default, also used for
ATR, is 0001 (Fi = 372). This value is used by the selected interface.
FDReg.6
FVAL.2
FDReg.5
FVAL.1
FDReg.4
FVAL.0
FDReg.3
DVAL.3
Refer to Table 93 above. This value is used to set the divide ratio used to
generate the smart card CLK. Default, also used for ATR, is 0001 (Di = 1).
FDReg.2
DVAL.2
FDReg.1
DVAL.1
FDReg.0
DVAL.0
This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register
are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is
created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rate is created
by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and
DI = 0001, the ratio of Fi/Di is 372/1. Thus the ETU divider is configured to divide by 2 * 372 = 744. The
maximum supported F/D ratio is 4096.
Table 92: Divider Ratios Provided by the ETU Counter
FI (code)
0000
0001
0010
0011
0100
0101
0110
0111
Fi (ratio)
372
558
744
1116
1488
1860
FCLK max
4
5
6
8
12
16
20
FI(code)
1000
1001
1010
1011
1100
1101
1110
1111
Fi(ratio)
512
512
768
1024
1536
2048
2048
FCLK max
5
5
7.5
10
15
20
20
DI(code)
0000
0001
0010
0011
0100
0101
0110
0111
Di(ratio)
1
1
2
4
8
16
32
DI(code)
1000
1001
1010
1011
1100
1101
1110
1111
Di(ratio)
12
20
16
16
16
16
16
16
Note: values marked with
⊕ are not included in the ISO definition and arbitrary values have been
assigned.
The values given below are used by the ETU divider to create the ETU clock. The entries that are not
shaded will result in precise CLK/ETU per ISO requirements. Shaded areas are not precise but are
within 1% of the target value.
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73S1209F-44MR/F/PD 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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