參數(shù)資料
型號(hào)： 73M1822-IM/F
廠商： Maxim Integrated Products
文件頁數(shù)： 31/82頁
文件大?。?/td> 0K
描述： MICRODAA VOICE DATA/FAX 42-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 260
系列： MicroDAA™
應(yīng)用： 傳真，調(diào)制解調(diào)器，尋呼機(jī)
接口： 串行
電源電壓： *
封裝/外殼： 42-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 42-QFN（8x8）
包裝： 管件
安裝類型： 表面貼裝
DS_1x22_017
73M1822/73M1922 Data Sheet
Rev. 1.6
37
6
Hardware Control Functions
This section describes the 73M1x22 capabilities with respect to its configuration and hardware pin control.
This includes features such as Interrupt Control, Power Management, Clock Control, General Purpose
Input/Output (GPIO) and control of the Call Progress Monitor.
6.1
Device Revision
The 73M1922 provides the device revision number for the Host-Side Device and the Line-Side Device.
For the 73M1822B07 and 73M1922A01 (73M1902B04) Host-Side Device, the current revision is 0111.
For the 73M1822B07 and 73M1922A01 (73M1912B07) Line-Side Device, the current revision is 1001.
Function
Mnemonic
Register
Location
Type
Description
REVHSDn
0x04[3:0]
R
Revision Host-Side Device
These read only status bits indicate the revision of the 73M1x22
Host-Side Device.
REVLSDn
0x1D[7:4]
R
Revision Line-Side Device
These read-only status bits provide the Device ID for the 73M1x22
Line-Side Device.
Before the barrier synchronization, the value is 0000.
After the barrier synchronization, the value represents the Device ID
of the Line-Side Device (73M1912).
6.2
Interrupt Control
The 73M1x22 supports a single interrupt that can be asserted under several configurable conditions. These
include status of GPIOs, RGMON, DET, SYNL and RGDT.
All interrupt sources that are enabled are OR’ed together to create the INT output signal. GPIO ports that
are configured to be output will not generate interrupts.
When the INT pin goes active (low), the host should read the interrupt source Register 0x03, which is then
cleared after the read operation. An interrupt during wake-on-ring should be interpreted as the detection of
a valid ring signal.
Address 0x03
Reset State E0h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
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