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724
5
FIGURE 2. Two-Port Isolation with Four 3650s.
Figure 2 illustrates how the 724 may provide isolated input
power to the input stage of four 3650s connected in the two-
port configuration. Power for the four output stages is
provided by the system +15VDC and –15VDC supplies.
Input stages are isolated from each other and from the
system supply. In this situation, the 724’s isolation specifi-
cation applies to amplifier’s input-to-output voltage and to
the voltage existing between any two I/P COM terminals.
ISOLATION VOLTAGE RATINGS
Since a “continuous” test is impractical in a product manu-
facturing situation (implies infinite test duration), it is gen-
erally accepted practice to perform a production test at a
higher voltage (i.e., higher than the continuous rating) for
some shorter length of time.
The important consideration is then “what is the relationship
between actual test conditions and the continuous derated
maximum specification” There are several rules of thumb
used throughout the industry to establish this relationship.
Burr-Brown has chosen a very conservative one: V
=
(2
x
V
) + 1000V. This relationship is appro-
priate for conditions where the system transient voltages are
not well defined.
(3)
Where the real voltages are well defined
or where the isolation voltage is not continuous the user may
choose to use a less conservative derating to establish a
specification from the test voltage.
SHORT CIRCUIT PROTECTION
The circuit in Figure 3 may be added to the input of the 724
to protect it from damage in situations where too much
current is demanded from the outputs—such as a short
circuit from an output to its common. The circuit limits input
current to approximately 150mA for an input voltage of
15VDC (for
β
of 2N2219 of 50).
NOTES: (1) “Output” denotes a single output terminal (+V or –V) and its
associated common. (2) “Channel” denotes a pair of outputs (+V and –V) and
their associated common. (3) Reference National Electrical Manufacturers
Association (NEMA) Standards Parts ICS 1-109 and ICS 1-111.
FIGURE 3. Short Circuit Protection.
P+
724
2N2219
IN4140
–
V
IN
+
100
1
V+
V–
E
R
1
0.47μF
3.6k
2
3
3
–V
O3
C
3
+V
O3
+V
O2
C
2
–V
O2
P+
V+
E
V–
V
IN
1.3k
0.47μF
+15VDC
COM
724
3
3
3
O/P COM
–15VDC
+
O
–
O
C
4
+
O
–
O
C
1
4
1
+15VDC
O/P COM
–15VDC
+15VDC
O/P COM
–15VDC
+15VDC
O/P COM
–15VDC
+15VDC
O/P COM
–15VDC
1 2 3 4 Denote four separate input commons.