參數(shù)資料
型號(hào): 71V424VL15YGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 512K X 8 STANDARD SRAM, 15 ns, PDSO36
封裝: 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-36
文件頁(yè)數(shù): 5/9頁(yè)
文件大?。?/td> 523K
代理商: 71V424VL15YGI
6.42
5
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
71V424S/L10
(2)
71V424S/L12
71V424S/L15
Symbol
Parameter
Min.
Max.
Mn.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
4
____
4
____
4
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
____
5
____
6
____
7
ns
t
OE
Output Enable to Output Valid
____
5
____
6
____
7
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
____
0
____
0
____
ns
t
OHZ
(1)
Output Disable to Output in High-Z
____
5
____
6
____
7
ns
t
OH
Output Hold from Address Change
4
____
4
____
4
____
ns
t
PU
(1)
Chip Select to Power Up Time
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power Down Time
____
10
____
12
____
15
ns
WRITE CYCLE
t
WC
Write Cycle Time
10
____
12
____
15
____
ns
t
AW
Address Valid to End of Write
8
____
8
____
10
____
ns
t
CW
Chip Select to End of Write
8
____
8
____
10
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
8
____
8
____
10
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
DW
Data Valid to End of Write
6
____
6
____
7
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
ns
t
OW
(1)
Output Active from End of Write
3
____
3
____
3
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z
____
6
____
7
____
7
ns
3622 tbl 10
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2. 0oC to +70oC temperature range only for low power 10ns (L10) speed grade.
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