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參數(shù)資料
| 型號(hào)： | 7140LA35CB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 1K X 8 DUAL-PORT SRAM, 35 ns, CDIP48 |
| 封裝： | SIDE BRAZED, DIP-48 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 153K |
| 代理商： | 7140LA35CB |
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but
is not production tested.
2. PLCC, TQFP and STQFP packages only.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/
W = VIL must occur after tBAA.
4. If
OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data
to be placed on the bus for the required tDW. If
OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
Symbol
Parameter
7130X20
(2)
7140X20
(2)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Unit
Min.
Max.
Min.
Max.
Min.
Max.
WRITE CYCLE
tWC
Write Cycle Time
(3)
20
____
25
____
35
____
ns
tEW
Chip Enable to End-of-Write
15
____
20
____
30
____
ns
tAW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
(4)
15
____
15
____
25
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
12
____
15
____
ns
tHZ
Output High-Z Time(1)
____
10
____
10
____
15
ns
tDH
Data Hold Time
0
____
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z
(1)
____
10
____
10
____
15
ns
tOW
Output Active from End-of-Write
(1)
0
____
0
____
0
____
ns
2689 tbl 10a
Symbol
Parameter
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Military
Unit
Min.
Max.
Min.
Max.
WRITE CYCLE
tWC
Write Cycle Time
(3)
55
____
100
____
ns
tEW
Chip Enable to End-of-Write
40
____
90
____
ns
tAW
Address Valid to End-of-Write
40
____
90
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
tWP
Write Pulse Width
(4)
30
____
55
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
40
____
ns
tHZ
Output High-Z Time(1)
____
25
____
40
ns
tDH
Data Hold Time
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z
(1)
____
25
____
40
ns
tOW
Output Active from End-of-Write
(1)
0
____
0
____
ns
2689 tbl 10b
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