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參數(shù)資料
| 型號： | 7140LA25PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 1K X 8 DUAL-PORT SRAM, 25 ns, PQFP64 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 149K |
| 代理商： | 7140LA25PFG |
11
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
NOTES:
1. R/
W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of
CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of
CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the HIGH impedance state.
6. Timing depends on which enable signal (
CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If
OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If
OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
OE
CE
R/
W
DATA OUT
DATA IN
tAS
(6)
tOW
tDW
tDH
tAW
tWP
(2)
tHZ
(7)
(4)
tWZ
(7)
tHZ
(7)
2689 drw 10
tWR
(3)
tWC
ADDRESS
CE
R/
W
DATA IN
tAS
(6)
tEW
(2)
tWR
(3)
tDW
tDH
tAW
2689 drw 11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 7140LA25PFG8 | 功能描述:靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 7140LA25PFI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 8K-Bit 1K x 8 25ns 64-Pin TQFP 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 8K-Bit 1K x 8 25ns 64-Pin TQFP Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 8KBIT 1KX8 25NS 64TQFP - Rail/Tube |
| 7140LA25PFI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 8K-Bit 1K x 8 25ns 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 8KBIT 1KX8 25NS 64TQFP - Tape and Reel |
| 7140LA35C | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 8KBIT 1KX8 35NS 48PIN SBDIP - Bulk |
| 7140LA35CB | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 8KBIT 1KX8 35NS 48PIN SBDIP - Bulk |
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