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參數(shù)資料
| 型號(hào)： | 70V34S20PFGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 18 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 211K |
| 代理商： | 70V34S20PFGI |
6.42
IDT70V35/34S/L
(IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
18
Timing Waveform of Write with BUSY
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the
BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
5624 drw 14
R/
W"A"
BUSY"B"
tWP
tWB
R/
W"B"
tWH
(2)
(3)
(1)
,
NOTES:
1.
tWH must be met for both master
BUSY input (slave) and output (master).
2.
BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3.
tWB is only for the slave version.
5624 drw 15
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS
tBAC
tBDC
(2)
5624 drw 16
ADDR"A"
ADDRESS "N"
ADDR"B"
BUSY"B"
tAPS
tBAA
tBDA
(2)
MATCHING ADDRESS "N"
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