參數資料
型號： 70824L35PFI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 4K X 16 STANDARD SRAM, 35 ns, PQFP80
封裝： TQFP-80
文件頁數： 3/21頁
文件大?。?/td> 191K
代理商： 70824L35PFI
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
11
Random Access Port: AC Electrical Characteristics Over
the Operating Temperature and Supply Voltage Range(2,4,5)
Random Access Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(2,4,5)
NOTES:
1. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not
production tested.
2. 'X' in part number indicates power rating (S or L).
3.
OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to
turn off and on the data to be placed on the bus for the required tDW. If
OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum
write pulse is the specified tWP. For the
CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4.
CMD access follows standard timing listed for both read and write accesses, (CE = VIH when CMD = VIL) or (CMD = VIH when CE = VIL).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Unit
Symbol
Parameter
Min.Max.Min.Max.Min.Max.Min.Max.
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
45
____
ns
tAA
Address Access Time
____
20
____
25
____
35
____
45
ns
tACE
Chip Enable Access Time
____
20
____
25
____
35
____
45
ns
tBE
Byte Enable Access Time
____
20
____
25
____
35
____
45
ns
tOE
Output Enable Access Time
____
10
____
10
____
15
____
20
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
3
____
ns
tCLZ
Chip Select Low-Z Time(1)
3
____
3
____
3
____
3
____
ns
tBLZ
Byte Select Low-Z Time(1)
3
____
3
____
3
____
3
____
ns
tOLZ
Output Enable Low-Z Time(1)
2
____
2
____
2
____
2
____
ns
tCHZ
Chip Select High-Z Time(1)
____
10
. ____
12
____
15
____
15
ns
tBHZ
Byte Select High-Z Time(1)
____
10
____
12
____
15
____
15
ns
tOHZ
Output Select High-Z Time(1)
____
9
____
11
____
15
____
15
ns
tPU
Chip Select Power-Up Time
0
____
0
____
0
____
0
____
ns
tPD
Chip Select Power-Down Time
____
20
____
25
____
35
____
45
ns
3099 tbl 20
Symbol
Parameter
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
WRITE CYCLE
tWC
Write Cycle Time
20
____
25
____
35
____
45
____
ns
tCW
Chip Enable to End-of-Write
15
____
20
____
25
____
30
____
ns
tAW
Address Valid to End-of-Write(3)
15
____
20
____
25
____
30
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
tWP
Write Pulse Width(3)
13
____
20
____
25
____
30
____
ns
tBP
Byte Enable Pulse Width(3)
15
____
20
____
25
____
30
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
tWHZ
Write Enable Output High-Z Time(1)
____
10
____
12
____
15
____
15
ns
tDW
Data Set-up Time
13
____
15
____
20
____
25
____
ns
tDH
Data Hold Time
0
____
0
____
0
____
0
____
ns
tOW
Output Active from End-of-Write
3
____
3
____
3
____
3
____
ns
3099 tbl 21
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