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| 型號(hào)： | 68HC05M68HC |
| 廠商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件頁(yè)數(shù)： | 60/130頁(yè) |
| 文件大小： | 1541K |
| 代理商： | 68HC05M68HC |
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Serial Input/Output Port (SIOP)
Advance Information
MC68HC705P6A
—
Rev. 2.0
60
Serial Input/Output Port (SIOP)
MOTOROLA
Figure 7-1. SIOP Block Diagram
7.3 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave
operation. No external mode selection inputs are available (for instance,
slave select pin).
7.3.1 Serial Clock (SCK)
The state of the SCK output normally remains a logic 1 during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time, the first bit of received data may
be presented at the SDI pin and the first bit of transmitted data is
presented at the SDO pin (see
Figure 7-2
). Data is captured at the SDI
pin on the rising edge of SCK. The transfer is terminated upon the eighth
rising edge of SCK.
The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is dependent upon the SPR0 and SPR1 bits located
in the mask option register. Refer to
11.3 Mask Option Register
for a
description of available SCK frequencies.
8-BIT
SHIFT
REGISTER
$0C
STATUS
REGISTER
BAUD
RATE
CONTROL
REGISTER
GENERATOR
HCO5 INTERNAL BUS
INTERNAL
CPU
CLOCK
SCK
SDI
SDO
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
I/O
$0B
$0A
CONTROL
LOGIC
SPE
SDI/PB6
SCK/PB7
SDO/PB5
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