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參數(shù)資料
| 型號(hào)： | 60-000-9203-000 |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1600 MHz, XMA |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 40K |
| 代理商： | 60-000-9203-000 |
SYNTHESIZERS
ABC
4726 Eisenhower Blvd Tampa, Florida 33634-6391
Telephone: +1 813-884-1411 Fax: +1 813-886-2794 http://www.trak.com
ELECTRICAL SPECIFICATIONS
Frequency Range:
0.4 to 4.95 GHz
Operating Bandwidth:
See Table 1
Output Power:
+ 8 dBm, minimum
Frequency Stability:
Same as Ref. input
Input Reference: Note 1
Frequency –
10 to 100 MHz
Power –
+ 3 to + 9 dBm
(Sine or TTL, 50 ohm)
Step Size:
200 kHz to 50 MHz
Switching Speed:
See Table II
Phase Noise:
See Figure 1
Output VSWR:
2.0:1, typical
Harmonics:
- 15 dBc, maximum
Spurious:
See Table II
Power Supply:
+ 14 to 18 volts
DC Current:
See Table I
BITE Scheme:
Phase Lock (“0” = lock)
Digital Control:
Parallel, TTL
ENVIRONMENTAL SPECIFICATIONS
Standard Operating Temperature:
0 to + 70 °C
(See Option - 002 for - 54 to + 85 °C.)
MECHANICAL SPECIFICATIONS
Size:
See Outline
RF Connectors:
SMA or GPO
OPTION
- 002 Extended Operating Temperature:
- 54 to + 85 °C
82
INDIRECT FREQUENCY SYNTHESIZERS
Series 60-000 Frequency Synthesizers are designed for
use in general purpose RF signal applications where
quick delivery is required.
60-000 Series
Note 1: K is a ratio of the input reference signal divided by the selected step size as defined below:
Group A: K = Ref. Signal
Step Size
Group B: K = 12 [Ref. Signal/Step Size)
Group C: K = 14 [Ref. Signal/Step Size)
K must be an even divisible and be a number over the range of 1 to 1023. The output noise will degrade if K
≤ 10.
Specifications are subject to change without notice.
Figure 1
Typical Phase Noise @1.0 GHz
200 kHz Step
10 MHz Step
SSB
Level
(dBc/Hz)
-50
-70
-90
-110
-130
-150
-170
1
5
10
100
1000
10000
Offset Frequency (kHz)
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