參數(shù)資料
型號： 5962R9584504VUC
英文描述： x8 SRAM
中文描述： x8的SRAM
文件頁數(shù)： 36/41頁
文件大小： 290K
代理商： 5962R9584504VUC
SIZE
A
5962-94663
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
B
SHEET
36
DSCC FORM 2234
APR 97
TABLE III. Pin descriptions - Continued.
Name
Type 1/
Active 2/
Description
Remote terminal address inputs
Remote Terminal Address bit 0. This is bit 0 of the RT address. This is the least
significant bit for the RT address.
RTA0
TUI
--
RTA1
RTA2
RTA3
RTA4
RTPTY
TUI
TUI
TUI
TUI
TUI
--
--
--
--
--
Remote Terminal Address bit 1. This is bit 1 of the RT address.
Remote Terminal Address bit 2. This is bit 2 of the RT address.
Remote Terminal Address bit 3. This is bit 3 of the RT address.
Remote Terminal Address bit 4. This is the most significant bit of the RT address.
Remote Terminal Parity. This is an odd parity input for the RT address.
JTAG testability pins
TDO. This output performs the operation of Test Data Output as defined in the IEEE
Standard 1149.1. This cell provides the output signal for the Test Access Port (TAP).
This non-inverting output buffer is optimized for driving TTL loads.
TDO
TTO
--
TCK
TI
--
TCK. This input performs the operation of Test Clock input as defined in the IEEE
Standard 1149.1. This cell provides the input clock for non-inverting input buffer that is
optimized for driving TTL input levels.
TMS
TUI
--
TMS. This input performs the operation of Test Mode Select as defined in the IEEE
Standard 1149.1. This cell provides the input signal for the Test Access Port (TAP).
This non-inverting input buffer is optimized for driving TTL input levels.
TDI
TUI
--
TDI. This input performs the operation of Test Data In as defined in the IEEE Standard
1149.1. This cell provides the input signal for the Test Access Port (TAP). This non-
inverting input buffer is optimized for driving TTL input levels.
TRST
TUI
AL
TRST
. This input provides the RESET to the TAP controller as defined in the IEEE
Standard 1149.1. This non-inverting input buffer is optimized for driving TTL input
levels. When not exercising JTAG, tie
TRST
to a logical 0.
Biphase inputs/outputs
CHA
DIO
DIO
--
--
Channel A (true). This is the Manchester-encoded true signal for channel A.
Channel A (complement). This is the Manchester-encoded complement signal for
channel A.
CHA
CHB
DIO
DIO
--
--
Channel B (true). This is the Manchester-encoded true signal for channel B.
Channel B (complement). This is the Manchester-encoded complement signal for
channel B.
CHB
DMA signals
DMAR
TTO 3/
AL
DMA Request. This signal is asserted when access to RAM is required. It goes inactive
upon request of the
DMAG
signal.
DMAG
TI
AL
DMA Grant. Once this input is received, the device is allowed to access RAM.
DMACK
TTO 3/
AL
DMA Acknowledge. This signal is asserted by the device to indicate the receipt of
DMAG
. The signal remains active until all RAM bus activity is completed.
DTACK
TI
AL
Data Transfer Acknowledge. This pin indicates that a data transfer is to occur and that
the device may complete the memory cycle.
See footnotes at end of table.
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