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參數(shù)資料
| 型號： | 5962F9863501VEC |
| 英文描述： | 3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference |
| 中文描述： | 四D型觸發(fā)器 |
| 文件頁數(shù)： | 9/41頁 |
| 文件大?。?/td> | 290K |
| 代理商： | 5962F9863501VEC |
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SIZE
A
5962-94663
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
D
SHEET
9
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Test conditions 1/
-55
°
C
≤
T
C
≤
+125
°
C
4.5 V
≤
V
DD
≤
5.5 V
unless otherwise specified
Device
type
Group A
subgroups
Min
Max
Unit
Functional tests
See 4.4.1b
All
7, 8
Register write timing
Address setup time 9/
t
a
All
9, 10, 11
0
Data setup time 9/
t
b
All
9, 10, 11
10
Data hold time 9/
t
c
All
9, 10, 11
8
Address hold time 9/
t
d
All
9, 10, 11
8
CS
↓
to
CS
↑
9/
t
e
All
9, 10, 11
105
Access delay 9/ 11/ 12/
t
f
All
9, 10, 11
85
RD/
WR
assertion to
CS
assertion 10/
t
g
All
9, 10, 11
0
CS
negation to
RD/
WR
negation 10/
t
h
All
9, 10, 11
0
CS
assertion to output
enable 9/
t
I
All
9, 10, 11
0
40
CS
negation to output
three-state 10/
t
j
V
CC
= minimum
See figure 5
All
9, 10, 11
5
35
ns
Register read timing
Address setup time 9/
t
a
All
9, 10, 11
0
CS
assertion to output
enable data valid 9/
t
b
All
9, 10, 11
95
CS
negation to output
disabled 10/
t
c
All
9, 10, 11
5
35
Address hold time 9/
t
d
All
9, 10, 11
0
CS
assertion to output
enable data invalid 9/
t
e
All
9, 10, 11
0
40
Access delay 9/ 11/ 12/
t
f
All
9, 10, 11
45
CS
↓
to
CS
↑
9/
t
g
V
CC
= minimum
See figure 5
All
9, 10, 11
105
ns
Memory write timing
01 – 06
10, 11
07, 08
09
All
9, 10, 11
0
18
Address propagation
delay
t
a
9, 10, 11
0
21
Address valid to
RCS
,
RWR
assertion 9/
t
b
V
CC
= minimum
See figure 5
9, 10, 11
15
35
ns
See footnotes at end of table.
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