參數(shù)資料
型號(hào)： 5962F9565402VCC
英文描述： Dual, 10-Bit, 40MHz, Current/Voltage Simultaneous-Output DACs
中文描述： 四2輸入異或（XOR）門(mén)
文件頁(yè)數(shù)： 16/41頁(yè)
文件大?。?/td> 290K
代理商： 5962F9565402VCC
SIZE
A
5962-94663
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
D
SHEET
16
DSCC FORM 2234
APR 97
TABLE IB. SEP test limits. 1/ 2/ 3/
V
DD
= 4.5 V
Device
type
T
A
=
Temperature
±
10
°
C
4/
Effective LET
no upsets
[MeV/(mg/cm
2
)]
Maximum device
cross section
LET = 120
(
μ
m
2
)
Bias for
latch-up test
V
DD
= 5.5 V
no latch-up
LET = 4/
04, 05
10, 11
+25
°
C
5/
5/
5/
1/
2/
3/
Devices that contain cross-coupled resistance must be tested at the maximum rated T
A
.
For SEP test conditions, see 4.4.4.5 herein.
Technology characterization and model verification supplemented by in-line data may be used in lieu of
end-of-line testing. Test plan must be approved by TRB and qualifying activity.
Worst case temperature T
A
= +125
°
C.
Values will be added when they become available. These devices have not yet been tested for SEP.
4/
5/
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