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參數(shù)資料
| 型號： | 5962F9565002VCC |
| 英文描述： | Quad 2-input NAND Gate |
| 中文描述： | 四2輸入與非門 |
| 文件頁數(shù)： | 12/41頁 |
| 文件大?。?/td> | 290K |
| 代理商： | 5962F9565002VCC |
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SIZE
A
5962-94663
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
D
SHEET
12
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Test conditions 1/
-55
°
C
≤
T
C
≤
+125
°
C
4.5 V
≤
V
DD
≤
5.5 V
unless otherwise specified
Device
type
Group A
subgroups
Min
Max
Unit
DMA timing - Continued
V
CC
= minimum
See figure 5
01 – 06
10, 11
07, 08
09
All
0
5
DMACK
assertion to
RAM control active
(negated)
t
h
9, 10, 11
-5
5
DMACK
negation to
address three-state 10/
t
i
9, 10, 11
5
DMACK
negation to RAM
control disabled 10/
t
j
All
9, 10, 11
5
ns
Power-up master reset timing
V
CC
= minimum
See figure 5
MRST
pulse width 10/
t
a
All
9, 10, 11
500
ns
MRST
negation to
ROMEN
assertion 10/
t
b
All
9, 10, 11
5
μ
s
MRST
negation to
READY
assertion 10/
t
c
All
9, 10, 11
10
μ
s
DMACK
negation to
ROMEN
negation 10/
t
d
All
9, 10, 11
500
ns
JTAG timing
TCK frequency
TCK period
TCK high time
TCK low time
TCK rise time
TCK fall time
TDI, TMS setup time
TDI, TMS hold time
TDO valid delay
All
All
All
All
All
All
All
All
All
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
1
MHz
ns
t
a
t
b
t
c
t
d
t
e
t
f
t
g
t
h
1000
1/2t
a
1/2t
a
5
5
250
250
250
See figure 5
Receiver electrical characteristics
V
CC
= minimum, see figure 5
Input f = 1 MHz (no transformer
in circuit)
Differential (receiver)
input impedance 10/
R
IZ
01, 03
04, 06
07, 09
10
1, 2, 3
15
k
01, 03
04, 06
07, 09
10
1, 2, 3
-10
+10
Common mode input
voltage 10/
V
IC
V
CC
= minimum, see figure 5
Direct-coupled stub, input
1.2 V
PP
, 200 ns rise/fall
time
±
25 ns, f = 1 MHz
02, 05
08, 11
1, 2, 3
-5
+5
V
See footnotes at end of table.
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