參數(shù)資料
型號： 5962F9562601QYC
英文描述： Low-Power, Serial, 12-Bit DACs with Force-Sense Voltage-Output
中文描述： x8胎膜早破
文件頁數(shù)： 10/41頁
文件大小： 290K
代理商： 5962F9562601QYC
SIZE
A
5962-94663
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
D
SHEET
10
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Test conditions 1/
-55
°
C
≤
T
C
≤
+125
°
C
4.5 V
≤
V
DD
≤
5.5 V
unless otherwise specified
Device
type
Group A
subgroups
Min
Max
Unit
Memory write timing – Continued
V
CC
= minimum
See figure 5
DTACK
setup time 9/
t
c
All
9, 10, 11
10
RCS
and
RWR
hold
time 9/ 13/
Data propagation delay
9/
Address hold time 9/
t
d
All
9, 10, 11
20
50
t
e
All
9, 10, 11
20
60
t
g
t
h
All
All
9, 10, 11
9, 10, 11
10
10
30
DTACK
hold time 9/
01 – 06
10, 11
07, 08
09
All
9, 10, 11
34
RWR
and
RCS
pulse
width (
DTACK
tied to
ground)
t
i
9, 10, 11
32
RWR
and
RCS
↑
to
DMACK
↑
10/
Data hold time 10/
t
j
9, 10, 11
15
125
t
k
All
9, 10, 11
10
40
ns
Memory read timing
01 – 06
10, 11
07, 08
09
All
9, 10, 11
0
18
Address propagation
delay
t
a
9, 10, 11
0
21
Address valid to
RCS
,
RRD
assertion 9/
t
b
9, 10, 11
15
35
DTACK
setup time 9/
t
c
All
9, 10, 11
10
RCS
and
RRD
hold
time 9/ 13/
Data setup delay 9/
t
d
All
9, 10, 11
20
50
01 - 06
07, 08
09
10, 11
01 – 06
10, 11
07, 08
09
All
9, 10, 11
12
9, 10, 11
10
t
e
9, 10, 11
14
9, 10, 11
0
Data hold delay
t
f
9, 10, 11
2
Address hold time 9/
t
g
V
CC
= minimum
See figure 5
9, 10, 11
10
30
ns
See footnotes at end of table.
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