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參數(shù)資料
| 型號(hào)： | 5962-9472501MCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | DUAL OP-AMP, 6000 uV OFFSET-MAX, 92 MHz BAND WIDTH, CDIP14 |
| 封裝： | DIP-14 |
| 文件頁數(shù)： | 2/27頁 |
| 文件大?。?/td> | 685K |
| 代理商： | 5962-9472501MCX |
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Application Division (Continued)
The disable feature of the CLC431 is such that DIS and DIS
have common-mode input voltage ranges of (+V
CC)to
(V
CC+3V) and are so guaranteed over the commercial
temperature range. Internal clamps (not shown) protect the
DIS input from excessive input voltages that could otherwise
cause damage to the device. This condition occurs when
enough source current flows into the node so as to allow DIS
to rise to V
CC. This clamp is activated once DIS exceeds DIS
by 1.5Volts and guarantees that V
DIS(ground referenced)
does not exceed 4.7Volts.
Figure 2 illustrates the differential mode of the CLC431’s
disable feature for ECL-type logic. In order for this mode to
operate properly, V
RTTL must be left floating while DIS and
DIS are to be connected directly to the ECL gate as illus-
trated. Applying a differential logic “high” (DIS - DIS
≥
0.4Volts) switches the tail current of the differential pair from
Q2 to Q1 and results in the disabling of that CLC431 chan-
nel. Alternatively, applying a differential logic “l(fā)ow” (DIS - DIS
≤ 0.4Volts) switches the tail current of the differential pair
from Q1 to Q2 and results in the enabling of that same
channel. The internal clamp, mentioned above, also protects
against excessive differential voltages up to 30 Volts while
limiting input currents to <3mA.
DC Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot be
cancelled and each contributes to the total DC offset voltage
at the output by the following equation:
VI
R
V
R
IR
offset
bn
s
f
g
io
f
g
bi
f
=±
+
++
+
11
(1)
The input resistor R
s is that resistance seen when looking
from the non-inverting input back towards the source. For
inverting DC-offset calculations, the source resistance seen
VRTTL
+VCC
DIS
Vnon-inv
Vinv
Vout
CLC431
100k
100k
Q1
Q2
TTL
CMOS
+
-
DS012712-27
FIGURE 1.
VRTTL
+VCC
DIS
Vnon-inv
Vinv
Vout
CLC431
100k
100k
Q1
Q2
TTL
CMOS
+
-
DS012712-27
FIGURE 2.
CLC431/432
www.national.com
10
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|---|---|
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