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參數(shù)資料
| 型號(hào)： | 5962-9469204QCA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | QUAD OP-AMP, 1500 uV OFFSET-MAX, 0.73 MHz BAND WIDTH, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁(yè)數(shù)： | 44/71頁(yè) |
| 文件大小： | 1709K |
| 代理商： | 5962-9469204QCA |
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TLC226x, TLC226xA
Advanced LinCMOS
RAIL-TO-RAIL
OPERATIONAL AMPLIFIERS
SLOS177D – FEBRUARY 1997 – REVISED MARCH 2001
49
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 5) and subcircuit in Figure 63 are generated using
the TLC226x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
.SUBCKT TLC226x 1 2 3 4 5
C1
11
12
3.560E–12
C2
6
7
15.00E–12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
43DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 21.04E6 –30E6 30E6 30E6 –30E6
GA
6
0
11
12 47.12E–6
GCM
0
6
10
99 4.9E–9
ISS
3
10
DC 8.250E–6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
RD1
60
11
21.22E3
RD2
60
12
21.22E3
R01
8
5
120
R02
7
99
120
RP
3
4
26.04E3
RSS
10
99
24.24E6
VAD
60
4
–.6
VB
9
0
DC 0
VC
3
53
DC .65
VE
54
4
DC .65
VLIM
7
8
DC 0
VLP
91
0
DC 1.4
VLN
0
92
DC 9.4
.MODEL DX D (IS=800.0E–18)
.MODEL JX PJF (IS=500.0E–15 BETA=281E–6
+ VTO= –.065)
.ENDS
VCC +
RP
IN –
2
IN +
1
VCC –
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
53
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
Figure 63. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
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